Semiconductor device enclosure and method of making same

Claim 2

An economical and highly reliable semiconductor device which can be made in standard enclosure outlines, said device comprising: a reinforced plastic board member of a selected peripheral shape having a major surface, a conductive pattern on said major surface, said pattern including a first portion, a second portion separated from the first portion by a space, at least one third portion interconnecting said first and second portions through said space, and at least two discrete portions in said space between said first and second portions, an aperture through said board member and pattern first portion, a metal heat sink member nested in said aperture and electrically connected to said pattern first portion, orientation means on said heat sink member, a semiconductor device element on said heat sink member having electrodes oriented in a predetermined manner with respect to said orientation means on said heat sink member, said heat sink member and said die oriented in a predetermined manner with respect to said discrete portions of said conductive pattern, a portion of each of said discrete pattern portions adpated for electrical interconnection with a die contact pad, a first housing terminal pin having a portion extending through said board member and elecTrically connected to one of said discrete pattern portions, a second housing terminal pin having a portion extending through said board member and electrically connected to the other of said discrete pattern portions, each of said die electrodes electrically connected to one of said discrete pattern portions, and a cup-shaped cover element of selected size affixed to said board member over said die, said discrete contacts and terminal pin portions.

Claim 3

An economical and highly reliable power semiconductor device which can be made in standard enclosure outlines, said device comprising: a reinforced plastic board member having two parallel major surfaces, a conductive pattern on one of said major surfaces, said pattern including a first portion, a second portion separated from the first portion by a space, at least one third portion interconnecting said first and second portions through said space and at least two discrete portions in said space between said first and second portions, an aperture through said board member and pattern first portion, a copper heat sink member nested in said aperture with opposite ends of the heat sink projecting beyond the planes on said major surfaces, said ends being flat and generally parallel said board member surfaces, a soldered connection between said heat sink member and said pattern first portion, orientation means on said heat sink member, a semiconductor device die soldered to the end of said heat sink member adjacent said one major surface, elongated mutually parallel wire bonding pads on said die oriented in a predetermined manner with respect to said orientation means on said heat sink member, said heat sink member and said die oriented in a predetermined manner with respect to said discrete portions of said conductive pattern, a discrete contact soldered to each of said discrete portions of said conductive pattern, a surface portion on each of said discrete contacts of the same metal as said die wire bonding pads, a first housing terminal pin having a portion extending through said board member and one of said discrete contacts, a second housing terminal pin having a portion extending through said board member and the other of said discrete contacts, a soldered connection between said terminal pin portions and their respective discrete contacts, a first filamentary wire of said same metal pressure bonded at one end to one of said die pads and at the other end to said surface portion of one of the contacts, a second filamentary wire of said same metal pressure bonded at one end to the other of said die pads and at the other end to said surface portion of the other of the contacts, and a cup-shaped cover element of selected size affixed to said board member surface over said die, filamentary wires, discrete contacts, and terminal pin portions.

Claim 4

An economical and highly reliable power semiconductor device which can be made in standard enclosure outlines, said device comprising: a reinforced plastic board member having two parallel major surfaces, a conductive pattern on one of said major surfaces, said pattern including a first portion, a second portion separated from the first portion by a space, at least one third portion interconnecting said first and second portions through said space and at least two discrete portions in said space between said first and second portions, an aperture through said board member and pattern first portion, a copper heat sink member nested in said aperture with opposite ends of the heat sink projecting beyond the planes on said major surfaces, said ends being flat and generally parallel said board member surfaces, a soldered connection between said heat sink member and said pattern first portion, orientation means on said heat sink member, a semiconductor device die soldered to the end of said heat sink member adjacent said one major surface, elongated mutually parallel wire bonding pads on said die oriented in a predetermined manner with respect to said orientation means on said heat sink member, said heat sink member and said die oriented in a predetermined manner with respect to said discrete portions of said conductive pattern, a discrete contact soldered to each of said discrete portions of said conductive pattern, a surface portion on each of said discrete contacts of the same metal as said die wire bonding pads, a first housing terminal pin having a portion extending through said board member and one of said discrete contacts, a second housing terminal pin having a portion extending through said board member and the other of said discrete contacts, a soldered connection between said terminal pin portions and their respective discrete contacts, a first filamentary wire of said same metal pressure bonded at one end to one of said die pads and at the other end to said surface portion of one of the contacts, a second filamentary wire of said same metal pressure bonded at one end to the other of said die pads and at the other end to said surface portion of the other of the contacts, and a cup-shaped cover element of selected size affixed to said board member surface over said die, filamentary wires, discrete contacts, and terminal pin portions.

Claim 5

An economical and highly reliable power transistor which can be made in standard enclosure outlines, said transistor comprising: a laminated reinforced plastic board member having two major parallel surfaces, a conductive pattern on one of said surfaces, said pattern including a central portion, a peripheral portion separated from the first portion by a space and covering the balance of said surface outside said space, portions interconnecting said central and peripheral portions through said space, and two discrete portions having elongated mutually parallel and partially overlapping areas in said space between said central and peripheral portions, an aperture through said board member and pattern central portion, a recess in the opposite surface of said board member surrounding said aperture, a generally cylindrical metal heat sink member in said aperture and electrically connected to said pattern central portion, knurled side surfaces on said heat sink member frictionally engaging said board member, flat ends on said heat sink Member perpendicular its longitudinal axis, a flange on one of said ends forming a shoulder that abuts said opposite major surface within said recess, said flange being about 0.002 - 0.01 inch thicker than said recess is deep, at least two flat and mutually parallel radial surfaces on said flange for orienting said heat sink member, a transistor die on said heat sink member having two elongated and mutually parallel contact pads oriented in a predetermined manner with respect to said flat surfaces on said heat sink member flange, said parallel die contact pads oriented generally perpendicular to said parallel areas of said pattern discrete portions, a discrete contact corresponding in size and shape to said pattern discrete portions registered on and soldered to each of said pattern discrete portions, a portion on each of said discrete contacts adapted for electrical interconnection with a die contact pad, a first housing terminal pin having a portion extending through said board member and through an aperture in one of said discrete contacts, a second housing terminal pin having a portion extending through said board member and through an aperture, each of said terminal pin portions soldered to their respective discrete contacts, parallel filamentary wires interconnecting said parallel die contact pads and said discrete contacts, and a cup-shaped cover element that is bonded to said board member surface between said first and second pattern portions, whereby said cover element encloses said die, said discrete contacts and terminal pin portions.

Claim 6

An economical and highly reliable power transistor which can be made in standard enclosure outlines, said transistor comprising: a laminated reinforced plastic board member having two major parallel surfaces, a conductive pattern on one of said surfaces, said pattern including a central portion, a peripheral portion separated from the first portion by a space and covering the balance of said surface outside said space, portions interconnecting said central and peripheral portions through said space, and two discrete portions having elongated mutually parallel and partially overlapping areas in said space between said central and peripheral portions, an aperture through said board member and pattern central portion, a recess in the opposite surface of said board member surrounding said aperture, a generally cylindrical metal heat sink member in said aperture and electrically connected to said pattern central portion, knurled side surfaces on said heat sink member frictionally engaging said board member, flat ends on said heat sink Member perpendicular its longitudinal axis, a flange on one of said ends forming a shoulder that abuts said opposite major surface within said recess, said flange being about 0.002 - 0.01 inch thicker than said recess is deep, at least two flat and mutually parallel radial surfaces on said flange for orienting said heat sink member, a transistor die on said heat sink member having two elongated and mutually parallel contact pads oriented in a predetermined manner with respect to said flat surfaces on said heat sink member flange, said parallel die contact pads oriented generally perpendicular to said parallel areas of said pattern discrete portions, a discrete contact corresponding in size and shape to said pattern discrete portions registered on and soldered to each of said pattern discrete portions, a portion on each of said discrete contacts adapted for electrical interconnection with a die contact pad, a first housing terminal pin having a portion extending through said board member and through an aperture in one of said discrete contacts, a second housing terminal pin having a portion extending through said board member and through an aperture, each of said terminal pin portions soldered to their respective discrete contacts, parallel filamentary wires interconnecting said parallel die contact pads and said discrete contacts, and a cup-shaped cover element that is bonded to said board member surface between said first and second pattern portions, whereby said cover element encloses said die, said discrete contacts and terminal pin portions.

Claim 7

An economical and highly reliable power transistor which can be made in standard enclosure outlines, said transistor comprising: a laminated paper phenolic board member having two parallel major surfaces, a conductive pattern on one of said surfaces, said pattern including a central portion, a peripheral portion separated from the first portion by a generally circular space and covering the balance of said surface outside said space, portions interconnecting said central and peripheral portions through said space and two discrete portions having elongated mutually parallel and partially overlapping areas in said space between said central and peripheral portions, an aperture through said board member and pattern central portion, a circular recess in the opposite surface of said board member surrounding said aperture and generally registered with said circular space on said one surface, a copper heat sink member nested in said aperture with opposite ends of the heat sink projecting beyond the planes of said surfaces, said ends being flat and parallel said board member surfaces, knurled side surfaces on said heat sink member frictionally engaging said board member, a soldered connection between said heat sink member and said pattern central portion, a flange on one flat end of said heat sink member aubtting said opposite surface of said board member within said recess, said flange being about 0.004 - 0.008 inch thicker than said recess is deep, a generally rectangular radial surface on said flange for orienting said heat sink member, a transistor die soldered to the end of said heat sink member adjacent said one board surface, parallel wire bonding pads on said die oriented in a predetermined manner with respect to said generally rectangular radial surface on said heat sink member flange, said parallel die wire bonding pads oriented perpendicular to said parallel areas of said pattern discrete portions, a discrete contact corresponding in size and shape to said pattern discrete portions registered on and soldered to each of said pattern discrete portions, a surface portion on each of said discrete contacts of the same metal as said die wire bonding pads, a first housing terminal pin having a portion extending through said board member and an aperture in one of said discrete contacts, a second housing terminal pin having a portion extending through said board member and an aperture in the other of said discrete contacts, a soldered connection between said terminal pin portions and their respective discrete contacts, a first filamentary wire of said same metal pressure bonded at one end to one of said die pads and at the other end to said surface portion of one of the contacts, a second filamentary wire of said same metal pressure bonded at one end to the other of said die pads and at the other end to said surface portion of the other of the contacts, said filamentary wires being generally perpendicular to said mutually parallel and partially overlapping areas of said discrete contacts, and a generally circular cup-shaped cover element having a lip that is bonded to said board member in said circular space between said first and second portions whereby said cover element encloses said die, filamentary wires, discrete contacts, and terminal pin portions.

Claim 8

An economical and highly reliable power transistor which can be made in standard enclosure outlines, said transistor comprising: a laminated paper phenolic board member having two parallel major surfaces, a conductive pattern on one of said surfaces, said pattern including a central portion, a peripheral portion separated from the first portion by a generally circular space and covering the balance of said surface outside said space, portions interconnecting said central and peripheral portions through said space and two discrete portions having elongated mutually parallel and partially overlapping areas in said space between said central and peripheral portions, an aperture through said board member and pattern central portion, a circular recess in the opposite surface of said board member surrounding said aperture and generally registered with said circular space on said one surface, a copper heat sink member nested in said aperture with opposite ends of the heat sink projecting beyond the planes of said surfaces, said ends being flat and parallel said board member surfaces, knurled side surfaces on said heat sink member frictionally engaging said board member, a soldered connection between said heat sink member and said pattern central portion, a flange on one flat end of said heat sink member aubtting said opposite surface of said board member within said recess, said flange being about 0.004 - 0.008 inch thicker than said recess is deep, a generally rectangular radial surface on said flange for orienting said heat sink member, a transistor die soldered to the end of said heat sink member adjacent said one board surface, parallel wire bonding pads on said die oriented in a predetermined manner with respect to said generally rectangular radial surface on said heat sink member flange, said parallel die wire bonding pads oriented perpendicular to said parallel areas of said pattern discrete portions, a discrete contact corresponding in size and shape to said pattern discrete portions registered on and soldered to each of said pattern discrete portions, a surface portion on each of said discrete contacts of the same metal as said die wire bonding pads, a first housing terminal pin having a portion extending through said board member and an aperture in one of said discrete contacts, a second housing terminal pin having a portion extending through said board member and an aperture in the other of said discrete contacts, a soldered connection between said terminal pin portions and their respective discrete contacts, a first filamentary wire of said same metal pressure bonded at one end to one of said die pads and at the other end to said surface portion of one of the contacts, a second filamentary wire of said same metal pressure bonded at one end to the other of said die pads and at the other end to said surface portion of the other of the contacts, said filamentary wires being generally perpendicular to said mutually parallel and partially overlapping areas of said discrete contacts, and a generally circular cup-shaped cover element having a lip that is bonded to said board member in said circular space between said first and second portions whereby said cover element encloses said die, filamentary wires, discrete contacts, and terminal pin portions.

Claim 9

An economical method of making highly reliable power semiconductor devices in standard enclosure outlines, said method comprising the steps of: forming a plurality of linearly arranged repetitive conductor patterns for a transistor enclosure base on a reinforced plastic circuit board member, said pattern for each package base comprising a first portion, a second portion spaced from the first portion, and at least one third portion interconnecting said first and second portions, and at least two discrete portions between said first and second portions, forming a heat sink element with two parallel flat end faces and orientation means with respect to said faces, orienting a plurality of said heat sinks in a predetermined manner, orienting a plurality of semiconductor device dies corresponding to said oriented heat sinks, mounting said oriented semiconductor dies on the faces of said oriented heat sinks to form a plurality of oriented element-heat sink subassemblies in which the element is electrically connected to said heat sink, blanking out a plurality of apertures in said circuit board with respect to each conductor pattern to define a plurality of linear frames containing a plurality of linearly arranged interconnected semiconductive device enclosure bases with each base having at least one aperture therein, cutting said linear frames from said board member, orienting a plurality of die-heat sink subassemblies with respect to said linear frame, press fitting oriented die-heat sink subassemblies into said apertures in said enclosure bases of said linear frame, electrically connecting said die-heat sink subassemblies to said pattern first portions, affixing at least two terminal pins to each of said enclosure bases with a portion of each of said terminal pins projecting through said circuit board and only one of said discrete portions of said conductive pattern, electrically connecting said pattern discrete portions, said terminal pin portions and electrodes on said dies, and affixing a cup-shaped cover element to said circuit board surface over said die, said heat sink, said electrical connections, and said terminal pin portions.

Claim 10

An economical method of making highly reliable power semiconductor devices in standard enclosure outlines, said method comprising the steps of: forming a plurality of linearly arranged repetitive conductor patterns for a transistor enclosure base on a reinforced plastic circuit board member, said pattern for each package base comprising a first portion, a second portion spaced from the first portion, and at least one third portion interconnecting said first and second portions, and at least two discrete portions between said first and second portions, forming a heat sink element with two parallel flat end faces and orientation means with respect to said faces, orienting a plurality of said heat sinks in a predetermined manner, orienting a plurality of semiconductor device dies corresponding to said oriented heat sinks, mounting said oriented semiconductor dies on the faces of said oriented heat sinks to form a plurality of oriented element-heat sink subassemblies in which the element is electrically connected to said heat sink, blanking out a plurality of apertures in said circuit board with respect to each conductor pattern to define a plurality of linear frames containing a plurality of linearly arranged interconnected semiconductive device enclosure bases with each base having at least one aperture therein, cutting said linear frames from said board member, orienting a plurality of die-heat sink subassemblies with respect to said linear frame, press fitting oriented die-heat sink subassemblies into said apertures in said enclosure bases of said linear frame, electrically connecting said die-heat sink subassemblies to said pattern first portions, affixing at least two terminal pins to each of said enclosure bases with a portion of each of said terminal pins projecting through said circuit board and only one of said discrete portions of said conductive pattern, electrically connecting said pattern discrete portions, said terminal pin portions and electrodes on said dies, and affixing a cup-shaped cover element to said circuit board surface over said die, said heat sink, said electrical connections, and said terminal pin portions.

Claim 11

An economical method of making a highly reliable power transistor in a standard outline comprising: forming a linearly arranged repetitive pattern for a transistor enclosure base in a conductive coating on a reinforced plastic circuit board member, said pattern for each enclosure base comprising a central portion, two discrete portions adjacent said central portion having elongated mutually parallel and partially overlapping areas, a peripheral portion spaced from and surrounding said central and discrete portions on the balance of said enclosure base, and at least one portion interconnecting said central and peripheral portions, forming a heat sink element with two parallel flat end faces and orientation means with respect to said faces, orienting a plurality Of said heat sinks in a predetermined manner, orienting a plurality of semiconductor device dies corresponding to said oriented heat sinks, mounting said oriented dies on the faces of said oriented heat sinks to form a plurality of oriented die-heat sink subassemblies in which the die is electrically connected to said heat sink, punching out a plurality of apertures in said circuit board member to define a linear frame containing a plurality of linearly arranged connected semiconductive device enclosure bases with said enclosure bases having a hole through said pattern central portion for receiving said assemblies, holes through said pattern peripheral portion for initially indexing said frame and for subsequently mounting said enclosure base on a support means, and a hole through each pattern discrete portion to receive enclosure terminal pins, orienting a plurality of said die-heat sink subassemblies with respect to said linear frame, press fitting die-heat sink subassemblies into said apertures in said pattern central portions of said enclosure bases of said linear frame, electrically connecting said die-heat sink assemblies to said pattern first portions, press fitting terminal pins into said holes in said pattern discrete portions with portions of said terminal pins projecting through said linear frame, placing a subassembly of two fuse-linked contacts corresponding in size and shape to said pattern discrete portions in register on said pattern discrete portions with said terminal pin portions projecting through apertures in said contacts, severing said fuse link between said contacts by passing an electrical current between said terminal pins, electrically connecting and securing together said contacts, said pattern discrete portions and said terminal pin portions, electrically connecting respective electrodes on said element to said contacts, and bonding a cup-shaped cover element to said circuit board surface between said pattern first and second portions to enclose said die, said contacts, said electrical connections and said terminal pin portions.

Claim 12

An economical method of making a highly reliable power transistor in a standard outline comprising: forming a linearly arranged repetitive pattern for a transistor enclosure base in a conductive coating on a reinforced plastic circuit board member, said pattern for each enclosure base comprising a central portion, two discrete portions adjacent said central portion having elongated mutually parallel and partially overlapping areas, a peripheral portion spaced from and surrounding said central and discrete portions on the balance of said enclosure base, and at least one portion interconnecting said central and peripheral portions, forming a heat sink element with two parallel flat end faces and orientation means with respect to said faces, orienting a plurality Of said heat sinks in a predetermined manner, orienting a plurality of semiconductor device dies corresponding to said oriented heat sinks, mounting said oriented dies on the faces of said oriented heat sinks to form a plurality of oriented die-heat sink subassemblies in which the die is electrically connected to said heat sink, punching out a plurality of apertures in said circuit board member to define a linear frame containing a plurality of linearly arranged connected semiconductive device enclosure bases with said enclosure bases having a hole through said pattern central portion for receiving said assemblies, holes through said pattern peripheral portion for initially indexing said frame and for subsequently mounting said enclosure base on a support means, and a hole through each pattern discrete portion to receive enclosure terminal pins, orienting a plurality of said die-heat sink subassemblies with respect to said linear frame, press fitting die-heat sink subassemblies into said apertures in said pattern central portions of said enclosure bases of said linear frame, electrically connecting said die-heat sink assemblies to said pattern first portions, press fitting terminal pins into said holes in said pattern discrete portions with portions of said terminal pins projecting through said linear frame, placing a subassembly of two fuse-linked contacts corresponding in size and shape to said pattern discrete portions in register on said pattern discrete portions with said terminal pin portions projecting through apertures in said contacts, severing said fuse link between said contacts by passing an electrical current between said terminal pins, electrically connecting and securing together said contacts, said pattern discrete portions and said terminal pin portions, electrically connecting respective electrodes on said element to said contacts, and bonding a cup-shaped cover element to said circuit board surface between said pattern first and second portions to enclose said die, said contacts, said electrical connections and said terminal pin portions.

Claim 13

An economical method of making a highly reliable power transistor in a standard enclosure outline comprising: etching a copper layer on the surface of a laminated paper phenolic circuit board member to form a linear repetitive conductor pattern or a transistor enclosure base, with the pattern for each enclosure base comprising a central portion, two discrete portions adjacent said central portion having elongated mutually generally parallel and partially overlapping areas, a peripheral portion spaced from and surrounding said central and discrete portions on the balance of said enclosure base, and portions interconnecting said central and peripheral portions, identically orienting a plurality of generally cylindrical copper heat sink elements having two parallel flat end faces with a circumferential flange contiguous one of said faces, orienting a wafer containing a plurality of mutually oriented power transistor dies, dicing said wafer while maintaining die orientation to form a plurality of mutually oriented dies, orienting a group of said plurality of power transistor dies with respect to the orientation of said plurality of heat sinks, progressively placing oriented dies from said group of oriented dies on an oriented end face of said plurality of oriented heat sinks and soldering them thereto to form a plurality of identically oriented die-heat sink subassemblies, punching out portions of said circuit board member to define a frame of two linear members with a plurality of aligned, partially formed transistor enclosure bases therebetween and to form in each enclosure base a hole through said pattern central portion, a hole through each of said pattern discrete portions and holes throgh said pattern peripheral portion coextensive with said linear members, identically orienting a group of said die-heat sink Subassemblies with respect to said linear frame, progressively press fitting oriented die-heat sink subassemblies into each of said apertures in said pattern central portion of said aligned enclosure bases, press fitting terminal pins into said holes in said pattern discrete portions, with terminal pin portions projecting through said linear frame, registering a subassembly of two fuse-linked pattern contacts corresponding in size and shape to said pattern discrete portions on said pattern discrete portions, with said terminal pin portions projecting through apertures in said contacts, simultaneously soldering together said heat sinks and pattern central portions, and said terminal pin portions, said pattern contacts and said pattern discrete portions, severing the fuse link between said pattern contacts by passing an electrical current between said terminal pins, pressure bonding a first filamentary wire between a contact pad on at least one of said dies and one of its two pattern contacts, indexing said frame using said holes in pattern peripheral portions, pressure bonding a second filamentary wire parallel and substantially overlapping the first between a second contact pad on said die and the other of its pattern contacts, bonding a lip of a cup-shaped cover element to said circuit board surface between said pattern first and second portions to enclose said die, said pattern contacts, said filamentary wires and said terminal pin portions, and punching out the remaining portions of said package base coextensive with said first linear members to produce an aligned linear array of discrete power transistors.

Claim 14

An economical method of making a highly reliable power transistor in a standard enclosure outline comprising: etching a copper layer on the surface of a laminated paper phenolic circuit board member to form a linear repetitive conductor pattern or a transistor enclosure base, with the pattern for each enclosure base comprising a central portion, two discrete portions adjacent said central portion having elongated mutually generally parallel and partially overlapping areas, a peripheral portion spaced from and surrounding said central and discrete portions on the balance of said enclosure base, and portions interconnecting said central and peripheral portions, identically orienting a plurality of generally cylindrical copper heat sink elements having two parallel flat end faces with a circumferential flange contiguous one of said faces, orienting a wafer containing a plurality of mutually oriented power transistor dies, dicing said wafer while maintaining die orientation to form a plurality of mutually oriented dies, orienting a group of said plurality of power transistor dies with respect to the orientation of said plurality of heat sinks, progressively placing oriented dies from said group of oriented dies on an oriented end face of said plurality of oriented heat sinks and soldering them thereto to form a plurality of identically oriented die-heat sink subassemblies, punching out portions of said circuit board member to define a frame of two linear members with a plurality of aligned, partially formed transistor enclosure bases therebetween and to form in each enclosure base a hole through said pattern central portion, a hole through each of said pattern discrete portions and holes throgh said pattern peripheral portion coextensive with said linear members, identically orienting a group of said die-heat sink Subassemblies with respect to said linear frame, progressively press fitting oriented die-heat sink subassemblies into each of said apertures in said pattern central portion of said aligned enclosure bases, press fitting terminal pins into said holes in said pattern discrete portions, with terminal pin portions projecting through said linear frame, registering a subassembly of two fuse-linked pattern contacts corresponding in size and shape to said pattern discrete portions on said pattern discrete portions, with said terminal pin portions projecting through apertures in said contacts, simultaneously soldering together said heat sinks and pattern central portions, and said terminal pin portions, said pattern contacts and said pattern discrete portions, severing the fuse link between said pattern contacts by passing an electrical current between said terminal pins, pressure bonding a first filamentary wire between a contact pad on at least one of said dies and one of its two pattern contacts, indexing said frame using said holes in pattern peripheral portions, pressure bonding a second filamentary wire parallel and substantially overlapping the first between a second contact pad on said die and the other of its pattern contacts, bonding a lip of a cup-shaped cover element to said circuit board surface between said pattern first and second portions to enclose said die, said pattern contacts, said filamentary wires and said terminal pin portions, and punching out the remaining portions of said package base coextensive with said first linear members to produce an aligned linear array of discrete power transistors.