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Patent US3790716A successfully refreshed from Google Patents.
US3790716A
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Synchronization circuit for a pcm-tdm exchange
Assignee: Alcatel Lucent NV
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Filing: 1971-12-06
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Granted: 1974-02-05
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Expires: 1991-12-06
Abstract
Abstract A channel synchronization control circuit is disclosed for a PCM telecommunication system in which for each group of trunks there is provided a synchronization circuit with data memories for each trunk. Each message is constituted by a plurality of digits equal to the number of trunks. Received message signals are stored in a buffer memory in which the time modification due to failure of channel synchronization can be corrected. The circuit continuously checks the channel synchronization and continuously applies such corrections as are necessary.
Inventors
- 👤 M Herry
- 👤 A Lejay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:30
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0629; H04Q; H04Q11/00; H04Q11/04; H04Q11/06
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
261 words
In a pulse code modulation switching system, a time division control including means for transmitting and receiving coded signals over a plurality of bi-directional trunks, said trunks being combined into groups, each group having a predetermined number of trunks with a predetermined plurality of channels per trunk, said signals comprising speech signals in the form of multi-bit serial binary messages, a data memory for each trunk, the data memories of a group being combined into a group memory, the invention comprising a plurality of synchronization control circuits with one such circuit being allotted to each group and with each such circuit having a plurality of time slot storage areas equal to the number of trunks in the group, said group memory including a group instruction memory for each group allotted to the synchronization circuit for that group, means for transmitting a plural digit synchronization code for each trunk group with channel data messages, said synchronization circuits including: means for continuously checking the synchronization code of a plurality of trunks and for continuously storing said code for each trunk in the respective group instruction memory, means for cyclically reading the group instruction memories for each group, means for cyclically coupling each instruction memory with the time slot storage areas of the synchronization circuit for that group, comparator means responsive to a predetermined plurality of errors between a synchronizing circuit and the group instruction memory for emitting an error signal, and a correction means modifying the time interval of the reading of the messages associated with any channel responsive to an error signal.
Claim 2
Dependent Claim
261 words
In a pulse code modulation switching system, a time division control including means for transmitting and receiving coded signals over a plurality of bi-directional trunks, said trunks being combined into groups, each group having a predetermined number of trunks with a predetermined plurality of channels per trunk, said signals comprising speech signals in the form of multi-bit serial binary messages, a data memory for each trunk, the data memories of a group being combined into a group memory, the invention comprising a plurality of synchronization control circuits with one such circuit being allotted to each group and with each such circuit having a plurality of time slot storage areas equal to the number of trunks in the group, said group memory including a group instruction memory for each group allotted to the synchronization circuit for that group, means for transmitting a plural digit synchronization code for each trunk group with channel data messages, said synchronization circuits including: means for continuously checking the synchronization code of a plurality of trunks and for continuously storing said code for each trunk in the respective group instruction memory, means for cyclically reading the group instruction memories for each group, means for cyclically coupling each instruction memory with the time slot storage areas of the synchronization circuit for that group, comparator means responsive to a predetermined plurality of errors between a synchronizing circuit and the group instruction memory for emitting an error signal, and a correction means modifying the time interval of the reading of the messages associated with any channel responsive to an error signal.
Claim 3
Dependent Claim
42 words
A system as claimed in claim 1, wherein each said data memory comprises a buffer memory associated with said correction means, and said correction means controls the timing of the reading of messages from said buffer memory responsive to an error signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-02-04 | 1977-08-06 | 1978-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-02-04 | 1981-08-06 | 1982-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-02-04 | 1985-08-06 | 1986-02-05 | $7700.00 | Window Closed / Lapsed |