Apparatus for deskewing data signals in a multi-track recording system

Claim 2

Apparatus for deskewing data signals in a multitrack recording system, for use with a plurality of sources of data signals, a plurality of sources of error signals and a source of timing signals, said apparatus comprising: a plurality of deskewing buffers each having first, second, third and fourth input terminals and first, second, third and fourth output terminals, said first input terminal of each of said buffers being coupled to a corresponding one of said sources of error signals, said second input terminal of each of said buffers being coupled to a corresponding one of said sources of data signals, said third input terminal of each of said buffers being coupled to said source of timing signals; a logic gate having a plurality of input leads and an output lead, said first output terminal of each of said buffers being connected to a corresponding one of said input leads of said gate; and means for coupling said output lead of said gate tO said fourth input terminal of each of said buffers.

Claim 3

Apparatus for deskewing as defined in claim 1 including: a multiple error detection circuit having an output lead and a plurality of input leads, said second output terminals of each of said buffers being connected to a corresponding one of said input leads of said error detection circuit.

Claim 4

Apparatus for deskewing as defined in claim 1 wherein said means for coupling includes: first and second flip-flops each having first, second and third input leads and first and second output leads, said first input lead of said first flip-flop being connected to said output lead of said gate, said source of timing signals being connected to said second input leads of said first and said second flip-flops, said first output lead of said first flip-flop being connected to said first input lead of said second flip-flop, said second output lead of said first flip-flop being connected to said third input lead of said second flip-flop, said first output lead of said second flip-flop being connected to said third input lead of said first flip-flop and to said fourth input terminal of each of said buffers.

Claim 5

Apparatus for deskewing as defined in claim 1 including: a multiple error detection circuit having an output lead and a plurality of input leads, said second output terminals of each of said buffers being connected to a corresponding one of said input leads of said error detection circuit; and wherein said means for coupling includes: first and second flip-flops each having first, second and third input leads and first and second output leads, said first input lead of said first flip-flop being connected to said output lead of said gate, said source of timing signals being connected to said second input leads of said first and said second flip-flops, said first output lead of said first flip-flop being connected to said first input lead of said second flip-flop, said second output lead of said first flip-flop being connected to said third input lead of said second flip-flop, said first output lead of said second flip-flop being connected to said third input lead of said first flip-flop and to said fourth input terminal of each of said buffers.

Claim 6

Apparatus for deskewing data signals in a multitrack recording system, for use with a plurality of sources of data signals, a plurality of sources of error signals and a source of timing signals, said apparatus comprising: a plurality of deskewing buffers each having first, second, third, fourth and fifth input terminals and first, second, third and fourth output terminals, said first input terminal of each of said buffers being coupled to a corresponding one of said sources of error signals, said second input terminal of each of said buffers being coupled to a corresponding one of said sources of data signals, said third input terminal of each of said buffers being coupled to said source of timing signals; a logic gate having a plurality of input leads and an output lead, said first output terminal of each of said buffers being connected to a corresponding one of said input leads of said gate; means for coupling said output lead of said gate to said fourth input terminal of each of said buffers; and a plurality of control oscillators each having an input lead and an output lead, said input lead of each of said oscillators being coupled to a corresponding one of said sources of data signals, said fifth input terminal of each of said buffers being connected to a corresponding one of said output leads of said oscillators.

Claim 7

Apparatus for deskewing data signals in a multitrack recording system, for use with a plurality of sources of data signals, a plurality of sources of error signals and a source of timing signals, said apparatus comprising: a plurality of deskewing buffers each having first, second, third, fourth and fifth input terminals and first, second, third and fourth output terminals, said first input terminal of each of said buffers being coupled to a corresponding one of said sources of error signals, said second input terminal of each of said buffers being coupled to a corresponding one of said sources of data signals, said third input terminal of each of said buffers being coupled to said source of timing signals; a logic gate having a plurality of input leads and an output lead, said first output terminal of each of said buffers being connected to a corresponding one of said input leads of said gate; means for coupling said output lead of said gate to said fourth input terminal of each of said buffers; and a plurality of control oscillators each having an input lead and an output lead, said input lead of each of said oscillators being coupled to a corresponding one of said sources of data signals, said fifth input terminal of each of said buffers being connected to a corresponding one of said output leads of said oscillators.

Claim 8

Apparatus for deskewing as defined in claim 5 including: a multiple error detection circuit having an output lead and a plurality of input leads, said second output terminal of each of said buffers being connected to a corresponding one of said input leads of said error detection circuit.

Claim 9

Apparatus for deskewing as defined in claim 5 wherein said means for coupling includes: first and seconD flip-flops each having first, second and third input leads and first and second output leads, said first input lead of said first flip-flop being connected to said output lead of said gate, said source of timing signals being connected to said second input leads of said first and said second flip-flops, said first output lead of said first flip-flop being connected to said first input lead of said second flip-flop, said second output lead of said first flip-flop being connected to said third input lead of said second flip-flop, said first output lead of said second flip-flop being connected to said third input lead of said first flip-flop and to said fourth input terminal of each of said buffers.

Claim 10

Apparatus for deskewing as defined in claim 5 including: a multiple error detection circuit having an output lead and a plurality of input leads, said second output terminal of each of said buffers being connected to a corresponding one of said input leads of said error detection circuit; and wherein said means for coupling includes: first and second flip-flops each having first, second and third input leads and first and second output leads, said first input lead of said first flip-flop being connected to said output lead of said gate, said source of timing signals being connected to said second input leads of said first and said second flip-flops, said first output lead of said first flip-flop being connected to said first input lead of said second flip-flop, said second output lead of said first flip-flop being connected to said third input lead of said second flip-flop, said first output lead of said second flip-flop being connected to said third input lead of said first flip-flop and to said fourth input terminal of each of said buffers.

Claim 11

Apparatus for deskewing data as defined in claim 5 wherein each of said buffers includes: first, second and third registers each having a plurality of cells, said first input terminal of said buffer being connected to said first register, said second input terminal of said buffer being connected to said third register, said third and said fourth input terminals of said buffer being coupled to each of said registers, and fifth input terminal of said buffer being coupled to said second register; and a plurality of gating means each having first and second input leads and an output lead, said gating means being divided into first and second groups, said first input lead of each of said gating means in said first group being connected to a corresponding one of said cells in said first register, said output lead of each of said gating means in said first group being connected to a following cell in said first register, said second input lead of each of said gating means in said first group being coupled to a corresponding one of said cells in said second register, said first input lead of each of said gating means in said second group being connected to a corresponding one of said cells in said third register, said output lead of each of said cells in said second group being connected to a following cell in said third register, said second input lead of each of said cells in said second group being coupled to a corresponding one of said cells in said second register.

Claim 12

A deskew buffer for a multi-track data recording system for use with a reset signal source, a source of data signals, a source of strobe signals, a source of timing signals and a source of error signals, said buffer comprising: a plurality of flip-flops each having first, second, third and fourth input leads and first and second output leads, said flip-flops being divided into first, second and third registers, said second input lead of each of said flip-flops being connected to said source of timing signals, said fourth input lead of each of said flip-flops being connected to said reset signal source, said first input lead of a first flip-flop in said second register being connected to said source of strobe signals; and a pluralitY of logic gates each having first and second input leads and an output lead, said gates being divided into first, second and third groups, said first input lead of a first gate in said first group being connected to said source of error signals, said output lead of said first gate in said first group being connected to said first input lead of a first flip-flop in said first register, said source of strobe signals being connected to said second input lead of said first gate in said first group and to said second input lead of a first gate in said third group, said second input lead of said first gate of said third group being connected to said source of data signals, said output lead of said first gate in said third group being connected to said first input lead of a first flip-flop in said third register, said first input lead of a first gate in said second group being connected to said first output lead of said first flip-flop in said first register, said second input lead of said first gate in said second group being connected to said second lead of a second flip-flop in said second register, said output lead of said first gate in said second group being connected to said first input leads of the second gates in said first and said third groups and to said first input lead of said second flip-flop in said second register, said second input lead of said second gate in said first group being connected to said first output lead of said first flip-flop in said third register, said output lead of said second gate in said first group being connected to said first input lead of a second flip-flop in said first register, said output lead of said second gate in said third group being connected to said first input lead of said second flip-flop in said third register.

Claim 13

A deskew buffer for a multi-track data recording system for use with a reset signal source, a source of data signals, a source of strobe signals, a source of timing signals and a source of error signals, said buffer comprising: a plurality of flip-flops each having first, second, third and fourth input leads and first and second output leads, said flip-flops being divided into first, second and third registers, said second input lead of each of said flip-flops being connected to said source of timing signals, said fourth input lead of each of said flip-flops being connected to said reset signal source, said first input lead of a first flip-flop in said second register being connected to said source of strobe signals; and a pluralitY of logic gates each having first and second input leads and an output lead, said gates being divided into first, second and third groups, said first input lead of a first gate in said first group being connected to said source of error signals, said output lead of said first gate in said first group being connected to said first input lead of a first flip-flop in said first register, said source of strobe signals being connected to said second input lead of said first gate in said first group and to said second input lead of a first gate in said third group, said second input lead of said first gate of said third group being connected to said source of data signals, said output lead of said first gate in said third group being connected to said first input lead of a first flip-flop in said third register, said first input lead of a first gate in said second group being connected to said first output lead of said first flip-flop in said first register, said second input lead of said first gate in said second group being connected to said second lead of a second flip-flop in said second register, said output lead of said first gate in said second group being connected to said first input leads of the second gates in said first and said third groups and to said first input lead of said second flip-flop in said second register, said second input lead of said second gate in said first group being connected to said first output lead of said first flip-flop in said third register, said output lead of said second gate in said first group being connected to said first input lead of a second flip-flop in said first register, said output lead of said second gate in said third group being connected to said first input lead of said second flip-flop in said third register.