Circuit arrangement for rhythmic, intermittent operation of separate magnets

Claim 2

A circuit arrangement for rhythmic, intermittent operation of separate magnets of a group, which can be selected by means of triggered semiconductor switches, characterized in that a monostable trigger circuit controlled by the time signals is provided for triggering the semiconductor switches and in that the capacitor of the trigger circuit is connected via an RCmember and a series resistor to the uncontrolled operational voltage of the separate magnets.

Claim 3

A circuit arrangement as claimed in claim 1, characterized in that the series resistor is divided into two resistors and the junction has connected to it the collector-emitter path of a load transistor, which can be controlled in accordance with the sum of the currents required for triggering the semiconductor switches.

Claim 4

A circuit arrangement as claimed in claim 2, characterized in that the thyristors are used as semiconductor switches and the gates thereof are each connected to a diode summation circuit, the resistors of which are connected to the base of the adjustable load transistor.

Claim 5

A circuit arrangement as claimed in claim 3, characterized in that for each gate of the thyristors a fixed bias voltage is provided and the selection conductor is connected via a diode to the bias voltage supply conductor and a diode connected in opposite sense relative to the diode of the selection conductor is provided in front of the gate.

Claim 6

A circuit arrangement for providing selected solenoids of a group of solenoids with electrical pulses having a uniform energy coNtent from an unstabilized source of voltage, comprising a plurality of semiconductor switches, each of said semiconductor switches having a control input for receiving solenoid selection signals and having a main conduction path selectively switchable from a normally high impedance to a lower impedance in response to a corresponding solenoid selection signal on the control input thereof, means connecting the main conduction path of each semiconductor switch in series with a separate solenoid, a monostable multivibrator means triggered by clock pulses and comprising a timing network including a capacitor connected to the unstabilized source of voltage for providing an output pulse having a duration varying as an inverse function of the magnitude of the unstabilized source of voltage, filter means comprising an R-C network connecting the timing network of the monostable multivibrator means to the unstabilized voltage source for providing a signal voltage to the timing network of the multivibrator that increases the pulse width of the multivibrator means as an inverse function of the unstabilized voltage, and sensing means connected to the control inputs of the semiconductor switches for providing a sensing signal to the timing network of the monostable multivibrator that increases the pulse width of the multivibrator as a direct function of the number of solenoid selection signals applied to the semiconductor switches, and energizing switch means connected to the multivibrator means for connecting all the series connected solenoids and semiconductor switches in parallel with the unstabilized source of voltage in response to the output pulse of the multivibrator.

Claim 7

A circuit arrangement for providing selected solenoids of a group of solenoids with electrical pulses having a uniform energy coNtent from an unstabilized source of voltage, comprising a plurality of semiconductor switches, each of said semiconductor switches having a control input for receiving solenoid selection signals and having a main conduction path selectively switchable from a normally high impedance to a lower impedance in response to a corresponding solenoid selection signal on the control input thereof, means connecting the main conduction path of each semiconductor switch in series with a separate solenoid, a monostable multivibrator means triggered by clock pulses and comprising a timing network including a capacitor connected to the unstabilized source of voltage for providing an output pulse having a duration varying as an inverse function of the magnitude of the unstabilized source of voltage, filter means comprising an R-C network connecting the timing network of the monostable multivibrator means to the unstabilized voltage source for providing a signal voltage to the timing network of the multivibrator that increases the pulse width of the multivibrator means as an inverse function of the unstabilized voltage, and sensing means connected to the control inputs of the semiconductor switches for providing a sensing signal to the timing network of the monostable multivibrator that increases the pulse width of the multivibrator as a direct function of the number of solenoid selection signals applied to the semiconductor switches, and energizing switch means connected to the multivibrator means for connecting all the series connected solenoids and semiconductor switches in parallel with the unstabilized source of voltage in response to the output pulse of the multivibrator.

Claim 8

A circuit arrangement as claimed in claim 5 wherein the timing network in the monostable multivibrator comprises two series connected resistors, the sensing means further comprising a transistor having a collector-emitter path connecting the junction of the two series connected resistors to a reference potential, the sensing means further comprising a summing circuit for adding the total number of solenoid selection signals on the control input of the semiconductor switches, and means for connecting the summing circuit to the transistor for controlling the conductivity of the transistor, whereby the duration of the multivibrator output pulse is controllable by the number of solenoid selection signals applied to the semiconductor switches.

Claim 9

A circuit arrangement as claimed in claim 6, wherein the semiconductor switches comprise thyristors, wherein the control inputs of the semiconductor switches comprise the gates of the thyristors, wherein the summing circuit comprises a diode summation network comprising diodes and resistors, and wherein the resistors of the diode summation network and connected to the base of the transistor.

Claim 10

A circuit arrangement as claimed in claim 7, wherein the gate of each thyristor is provided with a fixed bias voltage through a circuit diode polarized oppositely to an associated diode in the diode summation network.