Monolithic memory sense amplifier/bit driver having active bit/sense line pull-up

Claim 2

In a monolithic memory array having a plurality of storage cells electrically connected to a bit driving circuit, and having sensing means also electrically connected to said storage cell, said bit driving means inserting binary information into said storage cell by establishing a potential difference between a pair of bit/sense lines, the improvement comprising: a source of potential; an impedance; first and second transistors each having collector, base, and emitter, the collectors being electrically connected to said source of potential, the bases being electrically connected also to said source of potential through said impedance, each of the emitters being respectively connected to one of said pair of bit/sense lines.

Claim 3

Apparatus as in claim 1 in which said bases are electrically connected to said bit driving circuit biasing said transistors off during read or write operations such that the bases being electrically connected to said source of potential through said impedance and said collectors being electrically connected to said source of potential, essentially comprise diode connections between said source of potential and each of said bit lines for establishing a conductive current path between said source of potential and the one of the bit lines having a relatively lower potential.

Claim 4

A bit driver circuit for controlling the potential on two bit lines having a separate transistor coupling each of the bit lines to a reference potential when it is conducting; a first current switch circuit having transistors with their collectors coupled to the base of the first of the separate transistors and their emitters coupled to a first current source to bias the first of the separate transistors nonconducting when any one of the mentioned transistors in this first current switch are conducting; a second current switch circuit having transistors with their collectors coupled to the base of the second of the separate transistors and their emitters coupled to a second common current source to bias the second of the separate transistors nonconducting when any of the mentioned transistors in the second current switch circuit are conducting; a cross-coupling transistor with its emitter coupled to the first current source and its collector coupled to the base of the second of the separate transistors so that this crosscoupling transistor conducts while the mentioned transistors in the first current switch are all biaSed nonconducting to bias the second of the separate transistors off; and means for biasing the separate transistors on while they are not held off by the current switch circuits whereby a data signal need be supplied only to the first of the current switches, the improvement comprising: active pull up means coupling a potential source to one of the said two bit lines, during a write recovery cycle immediately following a write cycle.

Claim 5

A bit driver circuit for controlling the potential on two bit lines having a separate transistor coupling each of the bit lines to a reference potential when it is conducting; a first current switch circuit having transistors with their collectors coupled to the base of the first of the separate transistors and their emitters coupled to a first current source to bias the first of the separate transistors nonconducting when any one of the mentioned transistors in this first current switch are conducting; a second current switch circuit having transistors with their collectors coupled to the base of the second of the separate transistors and their emitters coupled to a second common current source to bias the second of the separate transistors nonconducting when any of the mentioned transistors in the second current switch circuit are conducting; a cross-coupling transistor with its emitter coupled to the first current source and its collector coupled to the base of the second of the separate transistors so that this crosscoupling transistor conducts while the mentioned transistors in the first current switch are all biaSed nonconducting to bias the second of the separate transistors off; and means for biasing the separate transistors on while they are not held off by the current switch circuits whereby a data signal need be supplied only to the first of the current switches, the improvement comprising: active pull up means coupling a potential source to one of the said two bit lines, during a write recovery cycle immediately following a write cycle.

Claim 6

A bit driver circuit as in claim 3 wherein the active pull up means coupling a potential source to one of the said two bit lines, during a write recovery cycle immediately following a write cycle comprises: an impedance; first and second transistors each having a collector, base, and emitter, the collectors being electrically connected to said source of potential through said impedance, each of the emitters being respectively connected to one of said pair of bit/sense lines.

Claim 7

A bit driver circuit as in claim 4 wherein each of said bases is electrically connected to said bit driving circuit biasing said transistors off during read or write operations such that the bases being electrically connected to said source of potential through said impedance and said collectors being also electrically connected through said source of potential, essentially comprise diode connections between said source of potential and each said bit lines for establishing a conductive current path between said source of potential and the one of the said bit lines having a relatively lower potential.