Electronic pulse amplifier circuits

Claim 2

A pulse amplifier comprising first and second means for amplifying pulses, each of said amplifying means having predetermined distributed capacitances associated therewith, means for interconnecting said first and second amplifying means to a common terminal for receiving operating energy, said first and second amplifying means being biased in normally nonconducting states, means for interconnecting said first and second amplifying means to a common energy return terminal, means for coupling an output of said first amplifying means to an input of said second amplifying means, means for applying to an input of said first amplifying means a pulse, said first and second amplifying means tandemly amplifying such pulse, and means, connected between said coupling means and said common return terminal, for drawing a current from said coupling means to charge said distributed capacitances in response to the termination of such pulse.

Claim 3

An electronic pulse, amplifier circuit, comprising first and second transistors of a first conductivity type and a third transistor of a second conductivity type, the collector of said third transistor connecting through a first electrical signal path to the base of said first transistor and the collector of said second transistor connecting through a second electrical signal path to the base of said first transistor, said first and third transistors having distributed collector-base capacitances; and means for applying to the base of said third transistor a first binary pulse of appropriate polarity and amplitude to drive said first transistor into a conducting state and said third transistor into a saturated conducting state, and for terminating said first pulse and applying to the base of said second transistor a second pulse of appropriate polarity and amplitude to drive said second transistor into a conducting state, thereby removing stored minority carriers from the base region of said third transistor and charging the distributed capacitances of said first and third transistors.

Claim 4

An electronic pulse, amplifier circuit, comprising first and second transistors of a first conductivity type and a third transistor of a second conductivity type, the collector of said third transistor connecting through a first electrical signal path to the base of said first transistor and the collector of said second transistor connecting through a second electrical signal path to the base of said first transistor, said first and third transistors having distributed collector-base capacitances; and means for applying to the base of said third transistor a first binary pulse of appropriate polarity and amplitude to drive said first transistor into a conducting state and said third transistor into a saturated conducting state, and for terminating said first pulse and applying to the base of said second transistor a second pulse of appropriate polarity and amplitude to drive said second transistor into a conducting state, thereby removing stored minority carriers from the base region of said third transistor and charging the distributed capacitances of said first and third transistors.

Claim 5

The circuit in accordance with claim 2 in which said applying means includes a fourth transistor of said first conductivity type, the collector of which is connected to the base of said third transistor and to the base of which is applied said first pulse, said first pulse driving said fourth transistor into a conducting state and the termination of said first pulse driving said fourth transistor into a nonconducting state.

Claim 6

The circuit in accordance with claim 3, further comprising means for applying a single voltage of appropriate magnitude and polarity to bias said first, second, third and fourth transistors in normally nonconducting states.

Claim 7

The circuit in accordance with claim 4 in which the means for applying a bias voltage further includes: means for applying said voltage through a third electrical signal path to the emitter of said third transistor; means for applying said voltage through a fourth electrical signal path to the collector of said fourth transistor; and means for applying said voltage through a fifth electrical signal path to the collector of said first transistor.

Claim 8

The circuit in accordance with claim 5 in which said first electrical signal path includes a diode poled in the same direction as the base-emitter junction of said first transistor, thereby allowing forward current to flow from the collector of said third transistor to the base of said first transistor.

Claim 9

The circuit in accordance with claim 6, further comprising a diode connecting between the emitter and base of said first transistor, such diode being oppositely poled with respect to the base-emitter junction of said first transistor.

Claim 10

The circuit in accordance with claim 7 in which an overdrive circuit is inCluded in the emitter circuitry of said fourth transistor and a biasing resistor is included in said fourth electrical signal path.

Claim 11

The circuit in accordance with claim 3 in which said applying means includes means for concurrently providing the binary inverse of a binary input pulse, whereby such binary inverse is said second pulse and such input pulse is said first pulse.

Claim 12

The circuit in accordance with claim 9 in which said providing means includes a seventh electrical signal path for coupling said first pulse to the base of said third transistor and a sixth electrical signal path for coupling said second pulse to the base of said second transistor.

Claim 13

The circuit in accordance with claim 10 in which said sixth signal path includes an overdrive circuit for decreasing the turn-on and turn-off times of said second transistor.