Transistorized current switch for memory systems

Claim 2

A transistorized current switch comprising a logic first stage for providing a plurality of logic inputs, a current switching second stage connected to said first stage and including first, second the third transistors each having base, emitter and collector electrodes, the emitter electrode of said first transistor coupled to the base electrode of said second transistor and the emitter electrode of said second transistor connected to the base electrode of said third transistor, first, second and third oppositely poled diodes interconnecting the emitter base junctions of each of said transistors, a pair of oppositely poled diodes connecting the base electrode of the first transistor of said three transistors stages to a source of potential, said second stage responsive to a predetermined logic input condition of said first stage for forming a closed circuit allowing current flow through said collector electrodes of said first and second transistors of said second stage to the emitter electrode of the third transistor of said three transistor stage.

Claim 3

The combination of claim 1 further including a shunt resistance for each of said first, second and third diodes. of the current switching stage.

Claim 4

The combination of claim 1 further including a further transistor coupled to each of the transistors of said second stage, said further transistor including an emitter electrode connected to a reference point, a base electrode connected to the output of said logic stage, and a collector electrode connected to the base electrode of said third transistor.

Claim 5

The combination of claim 1 wherein said logic stage includes two inputs and first, second, third and fourth transistors, said logic stage first transistor having an emitter electrode connected to a first logic input, a base electrode connected to a further potential source and a collector electrode connected to the base electrode of said logic stage second transistor, said logic stage third transistor having its emitter electrode connected to the other logic input, its base electrode connected to said further potential source, and its collector electrode connected to the base electrode of said logic stage fourth transistor, said logic stage second and fourth transistor collector electrodes respectively connected to said source of potential, and each of the emitter electrodes of said logic stage second and fourth transistors respectively connected to the base electrode of a fifth transistor, said logic stage fifth transistor having its emitter electrode connected to a source of reference potential, and its collector electrode connected to the base electrode of said third transistor of said three-transistor stage.