Threshold logic overflow detector for a three-input adder

Claim 2

A three-input adder overflow detector circuit comprising first and second busses; means for converting at least five input bits, each bit being converted into a unit of current conducted selectively through a predetermined one of the first and second busses; means responsive to the units of current conducted through the busses for producing predetermined potentials thereon; and first and second means respectively for comparing the potentials of the first and second busses with a reference potential and thereby determining the occurrence and polarity of any net overflows in the adder.

Claim 3

An overflow detector circuit in accordance with claim 1 wherein the comparing means each comprise a bistable circuit being constrained to a first stable state when at least a predetermined number of units of current are conducted in the relevant bus and being constrained to a second stable state when less than the predetermined number of units of current are conducted in the relevant bus.

Claim 4

An overflow detector circuit in accordance with claim 2 wherein the converting means comprise five elements, each converting an information bit to a unit of current conducted alternatively through a predetermined one of the first and second busses.

Claim 5

An overflow detector circuit in accordance with claim 2 wherein the converting means comprise four elements, each converting an information bit to a unit of current conducted alternatively through a predetermined one of the first and second busses; a fifth element converting an information bit to a unit of current selectively conducted through the first bus, and a sixth element converting an information bit to a unit of current selectively conducted through the second bus.

Claim 6

An overflow detector circuit in accordance with claim 2 wherein each bistable circuit is constrained to the first stable state when at least two units of current are conducted in the relevant bus and is constrained to the second stable state when less than two units of current are conducted in the relevant bus.

Claim 7

An overflow detector circuit in accordance with claim 5 wherein the converting means comprise first, second, and third storage-processor elements, each for converting an input-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, and fourth and fifth storage-processor elements, each for converting a carry-bit from the adder into a unit of current conducted alternatively through a predeteRmined one of the first and second busses.

Claim 8

An overflow detector circuit in accordance with claim 5 wherein the converting means comprise first, second, and third storage-processor elements, each for converting an input-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, a fourth storage-processor element for converting a sum-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, and a fifth storage-processor element for converting a carry-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses.

Claim 9

An overflow detector circuit in accordance with claim 5 wherein the converting means comprise first, second, and third storage-processor elements, each for converting an input-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, a fourth storage-processor element for converting a sum-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, a fifth storage-processor element for converting a first carry-bit from the adder into a unit of current selectively conducted through the first bus, and a sixth storage-processor element for converting a second carry-bit from the adder into a unit of current selectively conducted through the second bus.

Claim 10

An overflow detector circuit in accordance with claim 2 wherein each bistable circuit is constrained to the first stable state when at least four units of current are conducted in the relevant bus and is constrained to the second stable state when less than four units of current are conducted in the relevant bus.

Claim 11

An overflow detector circuit in accordance with claim 9 wherein the converting means comprise first, second, and third storage-processor elements, each for converting an input-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, and fourth and fifth storage-processor elements, each for converting a carry-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses.

Claim 12

An overflow detector circuit in accordance with claim 9 wherein the converting means comprise first, second, and third storage-processor elements, each for converting an input-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, a fourth storage-processor element for converting a sum-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, and a fifth storage-processor element for converting a carry-bit into a unit of current conducted alternatively through a predetermined one of the first and second busses.

Claim 13

An overflow detector circuit in accordance with claim 9 wherein the converting means comprise first, second, and third storage-processor elements, each for converting an input-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, a fourth storage-processor element for converting a sum-word sign-bit from the adder into a unit of current conducted alternatively through a predetermined one of the first and second busses, a fifth storage-processor element for converting a first carry-bit from the adder into a unit of current selectively conducted through the first bus, and a sixth storage-processor element for converting a second carry-bit from the adder into a unit of current selectively conducted through the second bus.

Claim 14

An adder overflow dEtector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the sum-word sign-bit; means for storing a carry-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when less than two units of current are conducted in the first bus and for assuming a second stable state when at least two units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when less than two units of current are conducted in the second bus and for assuming a second stable state when at least two units of current are conducted in the second bus.

Claim 15

An adder overflow dEtector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the sum-word sign-bit; means for storing a carry-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when less than two units of current are conducted in the first bus and for assuming a second stable state when at least two units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when less than two units of current are conducted in the second bus and for assuming a second stable state when at least two units of current are conducted in the second bus.

Claim 16

An adder overflow detector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or to the second bus depending upon the value of the sum-word sign-bit; means for storing a carry-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when at least four units of current are conducted in the first bus and for assuming a second stable state when less than four units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when at least four units of current are conducted in the second bus and for assuming a second stable state when less than four units of current are conducted in the second bus.

Claim 17

An adder overflow detector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or to the second bus depending upon the value of the sum-word sign-bit; means for storing a carry-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when at least four units of current are conducted in the first bus and for assuming a second stable state when less than four units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when at least four units of current are conducted in the second bus and for assuming a second stable state when less than four units of current are conducted in the second bus.

Claim 18

An adder overflow detector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the sum-word sign-bit; means for storing one carry-bit and for selectively conducting a unit of current through the first bus in response to the value of the one carry-bit; means for storing another carry-bit and for selectively conducting a unit of current through the second bus in response to the value of the other carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when less than two units of current are conducTed in the first bus and for assuming a second stable state when at least two units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when less than two units of current are conducted in the second bus and for assuming a second stable state when at least two units of current are conducted in the second bus.

Claim 19

An adder overflow detector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the sum-word sign-bit; means for storing one carry-bit and for selectively conducting a unit of current through the first bus in response to the value of the one carry-bit; means for storing another carry-bit and for selectively conducting a unit of current through the second bus in response to the value of the other carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when less than two units of current are conducTed in the first bus and for assuming a second stable state when at least two units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when less than two units of current are conducted in the second bus and for assuming a second stable state when at least two units of current are conducted in the second bus.

Claim 20

An adder overflow detector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the sum-word sign-bit; means for storing one carry-bit and for selectively conducting a unit of current through the first bus in response to the value of the one carry-bit; means for storing another carry-bit and for selectively conducting a unit of current through the second bus in response to the value of the other carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when at least four units of current are conducted in the first bus and for assuming a second stable state when less than four units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when at least four units of current are conducted in the second bus and for assuming a second stable state when less than four units of current are conducted in the second bus.

Claim 21

An adder overflow detector circuit comprising first and second busses; means for storing three addend-word sign-bits and for selectively steering each of three units of current alternatively through the first bus or the second bus depending upon the value of the addend-word sign-bits; means for storing a sum-word sign-bit and for selectively steering a unit of current alternatively through the first bus or the second bus depending upon the value of the sum-word sign-bit; means for storing one carry-bit and for selectively conducting a unit of current through the first bus in response to the value of the one carry-bit; means for storing another carry-bit and for selectively conducting a unit of current through the second bus in response to the value of the other carry-bit; means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon; a reference potential; bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when at least four units of current are conducted in the first bus and for assuming a second stable state when less than four units of current are conducted in the first bus; and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when at least four units of current are conducted in the second bus and for assuming a second stable state when less than four units of current are conducted in the second bus.

Claim 22

A threshold logic overflow detector circuit comprising first and second busses; means connected to the first and second busses in a first sense for converting sign-bits of addend-words into units of current conducted alternatively through the first and second busses depending upon the values of the sign-bits; means connected to the first and second busses in a complement of the first sense for converting a sign-bit of a sum-word into a unit of current conducted alternatively through the first and second bus depending upon the value of the sum-word sign-bit; means connected in the complementary sense to one of the busses for converting a carry-bit into a unit of current conducted selectively to that bus depending upon the value of the carry-bit; means responsive to the units of current conducted through the busses for producing predetermined potentials thereon; and first and second means respectively for comprising the potentials of the first and second busses with a reference potential and storing the results of the comparisons.

Claim 23

A threshold logic overflow detector circuit comprising first and second busses; means connected to the first and second busses in a first sense for converting sign-bits of addend-words into units of current conducted alternatively through the first and second busses depending upon the values of the sign-bits; means connected to the first and second busses in a complement of the first sense for converting a sign-bit of a sum-word into a unit of current conducted alternatively through the first and second bus depending upon the value of the sum-word sign-bit; means connected in the complementary sense to one of the busses for converting a carry-bit into a unit of current conducted selectively to that bus depending upon the value of the carry-bit; means responsive to the units of current conducted through the busses for producing predetermined potentials thereon; and first and second means respectively for comprising the potentials of the first and second busses with a reference potential and storing the results of the comparisons.