Patent US3789205A successfully refreshed from Google Patents.
US3789205A
Expired / Lapsed
US
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Method of testing mosfet planar boards
Assignee: International Business Machines Corp
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Filing: 1972-09-28
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Granted: 1974-01-29
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Expires: 1992-09-28
Abstract
Abstract A technique of testing a MOSFET planar board in which each of the chips on the planar board can be electronically isolated for individual testing. In MOSFET technology there are two off chip inverters between the output logic blocks and the pins. These are the preoff chip inverter and the off chip inverter. A NOR gate is formed by adding an additional input line to each of the preoff chip inverters of each of the chips on the board, and the output of each of the chips which are not to be tested are driven to logical ones by application of a positive logical level to this input line while no input is applied to the NOR gates on the outputs of the chip which is to be tested. In this manner, all inputs to the chip to be tested are at a one or high logical level, and for test purposes each input to the chip can be brought to a low logical level or left at a high logical level in accordance with the test pattern to be applied. Its output or reaction to the input test patterns is monitored in the normal manner by the chip tester. Through utilization of this technique, the same test patterns which might number three thousand can be applied to the chip such that even though it remains on the planar board it can be tested equivalent to new. In this manner, each chip can be tested and a defective chip on a planar board isolated without mechanically isolating the chips by breaking chip interconnections.
Inventors
- 👤 R James
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:34
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31915; G01R31/3185; G01R31/318505
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
111 words
A method of testing individual chips, having input lines and output lines, mounted on a planar board while said chips are interconnected in a manner so as to perform desired logical functions comprising the steps of: a. electronically isolating the said chip to be tested by application of control signals to logic means on said chip; b. applying test patterns to the input lines of said chip to be tested; c. monitoring the outputs appearing on said output lines of said chip to be tested which result from said input test patterns; and d. comparing said monitored outputs with predetermined expected outputs to determine whether said chip being tested is defective.
Claim 2
Independent Claim
111 words
A method of testing individual chips, having input lines and output lines, mounted on a planar board while said chips are interconnected in a manner so as to perform desired logical functions comprising the steps of: a. electronically isolating the said chip to be tested by application of control signals to logic means on said chip; b. applying test patterns to the input lines of said chip to be tested; c. monitoring the outputs appearing on said output lines of said chip to be tested which result from said input test patterns; and d. comparing said monitored outputs with predetermined expected outputs to determine whether said chip being tested is defective.
Claim 3
Dependent Claim
46 words
The method of testing of claim 1 wherein said step of electronically isolating said chip to be tested is accomplished by causing all of the output lines of all of said chips which are not to be tested to be driven to the same logical level.
Claim 4
Dependent Claim
34 words
The method of testing of claim 2 further wherein certain of said input lines of said chip to be tested are driven to a different logical level to correspond with said desired test patterns.
Claim 5
Dependent Claim
46 words
The method of testing of claim 3 wherein said step of electronically isolating said chip to be tested is accomplished by causing all of said output lines of all of said chips which are not to be tested to be driven to a high logical level.
Claim 6
Dependent Claim
32 words
The method of testing of claim 4 wherein said input lines of said chip to be tested are selectively driven to a low logical level to correspond with said desired test patterns.
Claim 7
Dependent Claim
67 words
The method of testing of claim 5 wherein said logic means is an output block associated with each of said chips and a control line connected to each of said output blocks and a first potential applied to the output blocks of all of said chips which are not to be tested and a second potential applied to said output block of said chip to be tested.
Claim 8
Dependent Claim
25 words
The method of testing of claim 6 wherein said first potential is said high logical level and said secoNd potential is said low logical level.
Claim 9
Dependent Claim
30 words
The method of testing of claim 7 wherein said output blocks are operative such that said application of said low logical level to said blocks will not affect their outputs.
Claim 10
Dependent Claim
124 words
A planar board having individual logic chips having input and output lines mounted thereon with said input and output lines being logically interconnected comprising: a. an output block connected in series with said output lines of each of said chips; b. means for selectively applying logical levels to said output blocks to cause all of said output lines except those from a chip to be tested to assume a common logical level; c. means for applying test patterns to one of said chips to be tested; d. means for monitoring the outputs appearing on said output lines of said chip to be tested; and e. means for comparing said monitored outputs with predetermined expected outputs to determine whether said chip being tested is defective.
Claim 11
Dependent Claim
124 words
A planar board having individual logic chips having input and output lines mounted thereon with said input and output lines being logically interconnected comprising: a. an output block connected in series with said output lines of each of said chips; b. means for selectively applying logical levels to said output blocks to cause all of said output lines except those from a chip to be tested to assume a common logical level; c. means for applying test patterns to one of said chips to be tested; d. means for monitoring the outputs appearing on said output lines of said chip to be tested; and e. means for comparing said monitored outputs with predetermined expected outputs to determine whether said chip being tested is defective.
Claim 12
Dependent Claim
21 words
The apparatus of claim 9 wherein said chip to be tested has a low logical level applied to its output block.
Claim 13
Dependent Claim
23 words
The apparatus of claim 10 wherein said output blocks include a NOR gate and an inverter connected to each of said output lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |