Patent US3789144A successfully refreshed from Google Patents.
US3789144A
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Method for compressing and synthesizing a cyclic analog signal based upon half cycles
Assignee: Eaton Corp
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Filing: 1971-07-21
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Granted: 1974-01-29
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Expires: 1991-07-21
Abstract
Abstract An improved method for compressing a cyclic analog signal in which adjacent positive and negative half cycles are similar, such as an audio signal, and for reconstructing or synthesizing a new analog signal from the compressed signal. The original signal is compressed by removing one of the positive or the negative half cycles and, in a preferred embodiment, digitizing the remaining half cycles. The new analog signal is generated by sequentially applying each half cycle to an output and simultaneously storing such applied half cycle in a memory. After a half cycle is applied to the output and prior to applying the next half cycle in the sequence, the stored half cycle is applied to the output at a reversed polarity to simulate the portion which was originally removed.
Inventors
- 👤 J Doyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:42
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/66
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
96 words
For a cyclic analog signal in which adjacent positive and negative half cycles are similar, an improved method for compressing said signal during transmission and synthesizing a similar signal at an output comprising the steps of: removing one of said positive and negative half cycles; transmitting the remaining other of said positive and negative half cycles to said output; and repeating at said output each transmitted half cycle prior to reception of the next half cycle, each of said transmitted half cycles being repeated at a polarity opposite from the polarity of said transmitted half cycles.
Claim 2
Dependent Claim
96 words
For a cyclic analog signal in which adjacent positive and negative half cycles are similar, an improved method for compressing said signal during transmission and synthesizing a similar signal at an output comprising the steps of: removing one of said positive and negative half cycles; transmitting the remaining other of said positive and negative half cycles to said output; and repeating at said output each transmitted half cycle prior to reception of the next half cycle, each of said transmitted half cycles being repeated at a polarity opposite from the polarity of said transmitted half cycles.
Claim 3
Dependent Claim
62 words
An improved method for compressing a cyclic analog signal during transmission and synthesizing a similar signal at an output, as set forth in claim 1, including the step of storing said transmitted half cycles in a memory and wherein said transmitted half cycles are repeated by reading each stored half cycle from said memory prior to storing the next transmitted half cycle.
Claim 4
Dependent Claim
49 words
An improved method for compressing a cyclic analog signal during transmission and synthesizing a similar signal at an output, as set forth in claim 2, wherein each stored half cycle is read from said memory in an order reversed from the order in which it was transmitted and stored.
Claim 5
Dependent Claim
46 words
An improved method for compressing a cyclic analog signal during transmission and synthesizing a similar signal at an output, as set forth in claim 2, wherein each stored half cycle is read from said memory in the same order in which it was transmitted and stored.
Claim 6
Dependent Claim
52 words
An improved method for compressing a cyclic analog signal during transmission and synthesizing a similar signal at an output, as set forth in claim 2, and including the step of modifying the phase relationship between said transmitted half cycles and said repeated half cycles more nearly to simulate the cyclic analog signal.
Claim 7
Dependent Claim
58 words
An improved method for compressing a cyclic analog signal during transmission and synthesizing a similar signal at an output, as set forth in claim 2, including the steps of digitizing said transmitted half cycles prior to transmission and converting said received half cycles and said repeated half cycles from a digital to an analog format at said output.
Claim 8
Dependent Claim
59 words
An improved method for compressing a cyclic analog signal during transmission and synthesizing a similar signal at an output, as set forth in claim 1, and including the steps of digitizing said transmitted half cycles prior to transmission and converting said received half cycles and said repeated half cycles from a digital to an analog format at said output.
Claim 9
Independent Claim
79 words
A method for synthesizing a cyclic analog signal from a sequence of half cycles to one polarity comprising the steps of: sequentially applying said half cycles to an output, simultaneously storing each half cycle applied to said output, and applying each stored half cycle to said output prior to applying the next half cycle in the sequence to said output, each stored half cycle being applied at a polarity opposite from the polarity of said sequence of half cycles.
Claim 10
Independent Claim
79 words
A method for synthesizing a cyclic analog signal from a sequence of half cycles to one polarity comprising the steps of: sequentially applying said half cycles to an output, simultaneously storing each half cycle applied to said output, and applying each stored half cycle to said output prior to applying the next half cycle in the sequence to said output, each stored half cycle being applied at a polarity opposite from the polarity of said sequence of half cycles.
Claim 11
Dependent Claim
51 words
A method for synthesizing a cyclic analog signal from a sequence of half cycles of one polarity, as set forth in claim 8, wherein each stored half cycle is applied to said output in a format reversed from the format in which the original half cycle is applied to said output.
Claim 12
Dependent Claim
47 words
A method for synthesizing a cyclic analog signal from a sequence of half cycles of one polarity, as set forth in claim 8, wherein each stored half cycle is applied to said output in the same format as the original half cycle is applied to said output.
Claim 13
Dependent Claim
52 words
A method for synthesizing a cyclic analog signal from a sequence of half cycles of one polarity, as set forth in claim 8, and including the step of modifying the phase relationship between the applied half cycles and the applied stored half cycles more nearly to simulate the original cyclic analog signal.
Claim 14
Dependent Claim
57 words
A method for synthesizing a cyclic analog signal from a sequence of half cycles of one polarity, as set forth in claim 8, wherein said sequence of half cycles are in a digitized format and further including the step of converting to an analog format said applied sequence of half cycles and said applied stored half cycles.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |