Logic detector apparatus

Claim 2

Logic detector apparatus for receiving a logic input signal and selectively detecting positive and negative voltage levels in said input signal with respect to ''''one'''' and ''''zero'''' reference levels in positive or negative logic modes, said logic detector apparatus comprising: a final NOR gate having four input leads and an output; four selection NOR gates each having an output connected to a respective input of said final NOR gate; two logic mode control inputs to said apparatus for selecting two of said selection NOR gates for respective operation in one of said positive or negative logic modes; two reference level control inputs to said apparatus for selecting two of said selection NOR gates for respective operation in detecting positive and negative voltage levels in said input signal with respect to one of said reference levels; means for coupling said logic mode control inputs and said reference level control inputs to the inputs of each of said selection NOR gates for selecting one of said selection NOR gates associated with one of said logic modes and one of said reference levels; comparator means for receiving said logic input signal; said comparator meanS including means for comparing said input signal with one of said reference levels and coupling respective outputs to two of said selection NOR gates and means for comparing said input signal with the other of said reference levels and coupling respective outputs to the other two of said selection NOR gates, and said output NOR gate providing an output responsive to said input signal being more or less positive than the respective reference level.

Claim 3

Logic Detector apparatus according to claim 1, wherein said comparator means includes respective operational amplifiers for comparing said input signal with each of said ''''zero'''' and ''''one'''' reference levels.

Claim 4

Logic detector apparatus according to claim 2, wherein said comparator means further includes inverter means for inverting the respective outputs of said operational amplifiers.

Claim 5

Logic detector apparatus according to claim 3, wherein said inverter means comprises respective inverter stages coupled intermediate the outputs of said operational amplifiers and the inputs of said selection NOR gates so that a first two of said selection NOR gates receive inputs representing an inverted output of a respective operational amplifier.

Claim 6

Logic detector apparatus according to claim 4, wherein said comparator means includes means for respectively coupling the outputs of said operational amplifiers to the respective inputs of a second two of said selection NOR gates to that said second two selection NOR gates receive inputs representing the output of said respective operational amplifiers.

Claim 7

Logic detector apparatus according to claim 5, including means for coupling said ''''zero'''' reference level to the negative input of one of said operational amplifiers, and means for coupling said ''''one'''' reference level to the positive input of the other of said operational amplifiers.

Claim 8

Logic detector apparatus according to claim 6, including means for interconnecting the positive input of said one operational amplifier with the negative input of said other operational amplifier.

Claim 9

Logic detecting apparatus for receiving a logic input signal and selectively detecting positive and negative voltage levels in said input signal with respect to ''''one'''' and ''''zero'''' reference levels in positive or negative logic modes, said logic detector apparatus comprising: a pair of operational amplifiers each having positive and negative inputs; means for coupling a ''''zero'''' reference level to the negative input of one of said operational amplifiers; means for coupling a ''''one'''' reference level to the positive input of the other of said operational amplifiers; means for coupling said logic input signal to the positive input of said one operational amplifier and to the negative input of said other operational amplifier; four selection NOR gates each having three inputs and an output; a first of said selection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to the ''''zero'''' reference levels in a positive logic mode; a second of said selection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to said ''''one'''' reference level in a positive logic mode; a third of said slection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to said ''''zero'''' reference level in a negative logic mode; a fourth of said selection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to said ''''one'''' reference levels in a negative logic mode; a pair of inverters each coupled respectively between one of said operational amplifiers and the inputs of said first and second selection NOR gates; means for respectively connecting the outputs of said operational amplifiers to the respectIve inputs of said third and fourth selection NOR gates in a noninverting manner; two control inputs (Logic Level and Logic Level Complement) to said apparatus, including means for connecting one of said control inputs to the inputs of said first and third selection NOR gates and for connecting the other of said control inputs to said second and fourth selection NOR gates; two other control inputs (Negative Logic and Negative Logic Complement) to said apparatus, including means for connecting one of said other control inputs to said first and second of said selective NOR gate and for connecting the other of said control inputs to said third and fourth of said selection NOR gates; said control inputs including means for selecting one of said selection NOR gates for responding to said logic input signal; and an output NOR gate having four inputs respectively connected to the outputs of said four selection NOR gates; said output NOR gate providing an output responsive to said input signal being more or less positive than the respective ''''zero'''' or ''''one'''' reference level.

Claim 10

Logic detecting apparatus for receiving a logic input signal and selectively detecting positive and negative voltage levels in said input signal with respect to ''''one'''' and ''''zero'''' reference levels in positive or negative logic modes, said logic detector apparatus comprising: a pair of operational amplifiers each having positive and negative inputs; means for coupling a ''''zero'''' reference level to the negative input of one of said operational amplifiers; means for coupling a ''''one'''' reference level to the positive input of the other of said operational amplifiers; means for coupling said logic input signal to the positive input of said one operational amplifier and to the negative input of said other operational amplifier; four selection NOR gates each having three inputs and an output; a first of said selection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to the ''''zero'''' reference levels in a positive logic mode; a second of said selection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to said ''''one'''' reference level in a positive logic mode; a third of said slection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to said ''''zero'''' reference level in a negative logic mode; a fourth of said selection NOR gates associated with detecting positive and negative voltage levels in said input signal with respect to said ''''one'''' reference levels in a negative logic mode; a pair of inverters each coupled respectively between one of said operational amplifiers and the inputs of said first and second selection NOR gates; means for respectively connecting the outputs of said operational amplifiers to the respectIve inputs of said third and fourth selection NOR gates in a noninverting manner; two control inputs (Logic Level and Logic Level Complement) to said apparatus, including means for connecting one of said control inputs to the inputs of said first and third selection NOR gates and for connecting the other of said control inputs to said second and fourth selection NOR gates; two other control inputs (Negative Logic and Negative Logic Complement) to said apparatus, including means for connecting one of said other control inputs to said first and second of said selective NOR gate and for connecting the other of said control inputs to said third and fourth of said selection NOR gates; said control inputs including means for selecting one of said selection NOR gates for responding to said logic input signal; and an output NOR gate having four inputs respectively connected to the outputs of said four selection NOR gates; said output NOR gate providing an output responsive to said input signal being more or less positive than the respective ''''zero'''' or ''''one'''' reference level.

Claim 11

Logic detector apparatus for receiving a logic input signal and selectively detecting positive and negative voltage levels in said input signal with respect to ''''one'''' and ''''zero'''' reference levels in positive or negative logic modes, said logic detector apparatus comprising: a final logic gate having four input leads and an output; four selection logic gates each having an output connected to a respective input of said final logic gate; two logic mode control inputs to said apparatus for selecting two of said selection logic gates for respective operation in one of said positive or negative logic modes; two reference level control inputs to said apparatus for selecting two of said selection logic gates for respective operation in detecting positive and negative voltage levels in said input signal with respect to one of said reference levels; means for coupling said logic mode control inputs and said reference level control inputs to the inputs of each of said selection logic gates for selecting one of said selection logic gates associated with one of said logic modes and one of said reference levels; comparator means for receiving said logic input signal; said comparator means including means for comparing said input signal with one of said reference levels and coupling respective outputs to two of said selection logic gates and means for comparing said input signal with the other of said reference levels and coupling respective outputs to the other two of said selection logic gates, and said output logic gate providing an output responsive to said input signal being more or less positive than the respective reference level.

Claim 12

Logic detector apparatus for receiving a logic input signal and selectively detecting positive and negative voltage levels in said input signal with respect to ''''one'''' and ''''zero'''' reference levels in positive or negative logic modes, said logic detector apparatus comprising: a final logic gate having four input leads and an output; four selection logic gates each having an output connected to a respective input of said final logic gate; two logic mode control inputs to said apparatus for selecting two of said selection logic gates for respective operation in one of said positive or negative logic modes; two reference level control inputs to said apparatus for selecting two of said selection logic gates for respective operation in detecting positive and negative voltage levels in said input signal with respect to one of said reference levels; means for coupling said logic mode control inputs and said reference level control inputs to the inputs of each of said selection logic gates for selecting one of said selection logic gates associated with one of said logic modes and one of said reference levels; comparator means for receiving said logic input signal; said comparator means including means for comparing said input signal with one of said reference levels and coupling respective outputs to two of said selection logic gates and means for comparing said input signal with the other of said reference levels and coupling respective outputs to the other two of said selection logic gates, and said output logic gate providing an output responsive to said input signal being more or less positive than the respective reference level.