Pushbutton electronic pulsing dial

Claim 2

A telephone digit generator for generating dial pulses on a telephone line in response to a digit selected on a pushbutton pad at a telephone station set, said generator comprising: a. a non-destructive read-write memory, b. a read address register and a write address register, c. means for coding and loading the digit selected on the pushbutton pad into said memory at an address stored in the write address register, d. a presettable counteR arranged to receive data from said memory in response to a read signal, said counter having a plurality of counter stages, e. a read-write interlace means for generating a read signal, in response to a difference in the address stored in the read address register and the address stored in the write address register, when no digit is being selected on the pushbutton pad, f. a pulse generator for generating dial-pulse timing signals, g. means for generating a first enable signal in response to a difference in the state of at least one of the presettable counter stages, h. means responsive to every occurrence of the first enable signal for gating dial-pulse-timing signals into the presettable counter, i. dial pulse generating means responsive to dial-pulse-timing signals and to odd numbered occurrences of the first enable signal, for generating dial pulses on the telephone line, j. means, responsive to even numbered occurrences of the first enable signal, for loading a fixed data word into the presettable counter and for inhibiting the dial pulse generating means, whereby the digit selected is generated by interrupting telephone line current at the dial-pulse-timing signal rate as the dial-pulse-timing signals are fed into the presettable counter until all the presettable counter stages read the same state, and whereby the interdigit pause is provided by loading the presettable counter with a fixed data word to generate an even numbered occurrence of the first enable signal and gate dial-pulse-timing signals into the presettable counter until all of the presettable counter stages reach the same state.

Claim 3

The invention as defined in claim 1 wherein the means for generating the first enable signal is a logic gate having a plurality of inputs, each input of said logic gate being connected to monitor a corresponding counter stage of the presettable counter.

Claim 4

The invention as defined in claim 1 wherein the means for gating dial-pulse-timing signals into the presettable counter is a first dual input gate, one input of said gate being connected to the pulse generator and the other input of said gate being connected to receive the first enable signal.

Claim 5

The invention as defined in claim 1, wherein the dial pulse generating means includes a second dual input gate, one input of said gate being responsive to dial-pulse-timing signals and the other input of said gate being responsive to an enable signal derived from odd numbered occurrences of the first signal, the output of said dual input gate supplying a control signal for circuitry used to interrupt the telephone line current.

Claim 6

The invention as defined in claim 1 wherein the write address register and the read address register are counters, the sum in each counter corresponding to a particular location in said memory, and wherein after accessing said memory at the address stored in either the write address register of the read address register, the address stored in the last called register is automatically incremented.

Claim 7

The invention as defined in claim 1 wherein the dial-pulse-timing signals have a mark-to-space ratio compatible with central office receiving equipment designed for rotary mechanical dials.

Claim 8

The invention as defined in claim 1 wherein the fixed data word corresponds to a particular number, the time required for the presettable counter to count said particular number serving to measure the time alloted by the telephone digit generator for interdigit pauses.

Claim 9

The invention as defined in claim 1 wherein the digit selected is stored in said memory in Binary Coded Decimal form and wherein the inverse of the digit stored in said memory is loaded into the presettable counter if said counter is an up-counter.

Claim 10

The invention as defined in claim 1 wherein the means for generating the first enable signal is a logic gate having a plurality of inputs, each input of said logic gate being connected to monitor a corresponding counter stage of the presettabLe counter and wherein the means for gating dial-pulse-timing signals into the presettable counter is a first dual input gate, one input of said gate being connected to receive dial-pulse-timing signals from the pulse generator and the other input of said gate being connected to receive the first enable signal.

Claim 11

The invention as defined in claim 9 wherein said logic gate is at least a four input NOR gate and said first dual input gate is a dual input NOR gate.

Claim 12

The invention as defined in claim 1 wherein the read-write interlace means includes a comparator which compares the address stored in the read address register with the address stored in the write address register to determine whether all digits stored in said memory have been read and generated on the telephone line before generating a read signal, and wherein the trailing edge of the read signal is used to increment the address stored in the read address register.

Claim 13

A telephone digit generator for generating dial pulses on a telephone line in response to a digit selected on a pushbutton pad at a telephone station set, said generator comprising: a. a non-desctructive read-write memory, b. a read address register and a write address register, c. means for coding and loading the digit selected on the pushbutton pad into said memory at an address stored in the write address register, d. a presettable counter arranged to receive data from said memory, at an address stored in the read address register, in response to a load signal, said counter having a plurality of counter stages, e. a pulse generator for generating dial-pulse-timing signals f. means for generating a first enable signal in response to a difference in the state of at least one of the presettable counter stages g. first means responsive to the first enable signal for gating dial-pulse-timing signals into the presettable counter and second means, responsive to the first enable signal, for generating a second enable signal, h. third means, responsive to a difference in the address stored in the read address register and the address stored in the write address register, for generating a try-to-read signal, i. a read-write interlace means for generating a read signal, in response to the try-to-read signal, when no digit is being selected on the pushbutton pad, j. fourth means responsive to dial-pulse-timing signals and to the second enable signal, for generating dial pulses on the telephone line, k. fifth means, responsive to the read signal for generating a load signal, l. sixth means, responsive to every second occurrence of the first enable signal for inhibiting the second enable signal and for loading a fixed data word into the presettable counter, whereby to generate the digit selected, the telephone line current is interrupted under control of the dial-pulse-timing signals for the duration of the second enable signal and whereby following the end of the second enable signal, the interdigit pause is provided by loading the presettable counter with the fixed data word so as to generate another first enable signal and gate dial-pulse-timing signals into the presettable counter until all of the presettable counter stages reach the same state.

Claim 14

A telephone digit generator for generating dial pulses on a telephone line in response to a digit selected on a pushbutton pad at a telephone station set, said generator comprising: a. a non-desctructive read-write memory, b. a read address register and a write address register, c. means for coding and loading the digit selected on the pushbutton pad into said memory at an address stored in the write address register, d. a presettable counter arranged to receive data from said memory, at an address stored in the read address register, in response to a load signal, said counter having a plurality of counter stages, e. a pulse generator for generating dial-pulse-timing signals f. means for generating a first enable signal in response to a difference in the state of at least one of the presettable counter stages g. first means responsive to the first enable signal for gating dial-pulse-timing signals into the presettable counter and second means, responsive to the first enable signal, for generating a second enable signal, h. third means, responsive to a difference in the address stored in the read address register and the address stored in the write address register, for generating a try-to-read signal, i. a read-write interlace means for generating a read signal, in response to the try-to-read signal, when no digit is being selected on the pushbutton pad, j. fourth means responsive to dial-pulse-timing signals and to the second enable signal, for generating dial pulses on the telephone line, k. fifth means, responsive to the read signal for generating a load signal, l. sixth means, responsive to every second occurrence of the first enable signal for inhibiting the second enable signal and for loading a fixed data word into the presettable counter, whereby to generate the digit selected, the telephone line current is interrupted under control of the dial-pulse-timing signals for the duration of the second enable signal and whereby following the end of the second enable signal, the interdigit pause is provided by loading the presettable counter with the fixed data word so as to generate another first enable signal and gate dial-pulse-timing signals into the presettable counter until all of the presettable counter stages reach the same state.

Claim 15

The invention as defined in claim 12 wherein the means for generating the first enable signal is a logic gate having a plurality of inputs, each input of said logic gate being connected to monitor a corresponding counter stage of the presettable counter and wherein the means for gating dial-pulse-timing signals into the presettable counter is a first dual input gate, one input of said gate being connected to receive dial-pulse-timing signals from the pulse generator and the other input of said gate being connected to receive the first enable signal.

Claim 16

The invention as defined in claim 12 wherein the read-write interlace means includes a comparator which compares the address stored in the read address register with the address stored in tHe write address register to determine whether all digits stored in said memory have been read and generated on the telephone line before generating a read signal, and wherein the trailing edge of the read signal is used to increment the address stored in the read address register.