Multiplexing arrangement for a communication switching system

Claim 1

Multiplexing apparatus coupling a plurality of registerjunctors to two common logic units in a communication switching system, wherein the two common logic units are duplicates of each other and are normally operated in synchronism, but may be reconfigured to operate with either one active and the other offline; wherein the system includes a timing generator which supplies cyclically receiving time slot signals, with each register-junctor having an individual time slot; said multiplexing apparatus comprises a plurality of groups; each group comprises a plurality of buffers each individual to a register-junctor, two switch circuits which are duplicates of each other, a fan-out circuit, and a scanning circuit; means to couple timing signal leads from said timing generator and control signal leads from the two common logic units respectively to the two switch circuits in each group, the leads being coupled in multiple to all groups; the two switch circuits of each group include a configuration bistable device common to the two configuration control leads from the two common logic units coupled individually to the groups to set the configuration bistable device to select one of the switch circuits for that group, individual group timing signal leads from the timing generators of the two common logic units coupled to the respective switch circuits in each group, selection gate means (613) in each switch circuit of each group to enable it in response to the configuration bistable device being set for that switch circuit and receipt of a timing signal lead, and gate means connected to the selection gate means and to the multiple timing signal leads and control signal leads from the corresponding common logic unit to couple the signal conditions to outputs of the switch circuit; the fan-out circuit of each group having inputs from both switch circuits to couple the outputs of an enabled switch circuit to all the buffers of the group, and certain timing signals to the scanning circuit; the buffer circuits each comprise a plurity of control bistable devices having inputs coupled to outputs of the fan-out circuits of the group to reset and selectively set them during the individual time slot of the associated register-junctor in accordance with the signals on the control leads, outputs of the control bistable devices being coupled to the associated register-junctor; at least one scan lead from each register-junctor coupled to its individual buffer, a scan gate in each buffer enabled during the individual time slot of its register-junctor to couple the signal condition on said scan lead to an input of the scanning circuit of the group; the scanning circuit of each group comprises scan bistable devices, one of which is selectively set in accordance with the signal condition on the input from tHe buffer whose time slot is occurring; all of the scan bistable devices being reset toward the end of each time slot, the set and reset being controlled by timing signals from the fan-out circuit of the group; OR function means for each scanning circuit to supply a group common scan output to each common logic unit for said one scan lead signal from the register-junctors; and common OR function means in each common logic unit to supply a system common scan output for said one scan lead signal from the register-junctors for use in that common logic unit.