Claim 1
Independent Claim
69 words
The process for fabricating a collector self-isolated semiconductor integrated circuit structure of claim 1, wherein said epitaxial layer of said first conductivity type is formed with a concentration level of approximately 1016 atoms per cubic centimeter and wherein the base region of said first conductivity type is formed with a concentration level in the range of 1018 atoms per cubic centimeter to 5 X 1018 atoms per cubic centimeter.
Claim 2
Dependent Claim
731 words
However, since the base region 207 has a much higher impurity concentration than the P-type epitaxial layer 213, diffusion penetration of base region 207 by emitter region 209 is substantially less. In other words, the speed at which collector contact region 203 diffuses into epitaxial layer 213 is faster than the diffusion of emitter region 209 into base region 207. Various impurities may be used in this diffusion process such as arsenic, antimony or phosphorous. If phosphorous atoms are used as the impurity during the emitter diffusion, push out effect requires deeper penetration of emitter diffusion. This insures that collector contact 203 will reach buried region 201. For certain designs of emitter diffusion, collector contact 203 does not punch through the P-type epitaxial layer 213; in such a case, a bias of a few volts on the substrate 211 will respect to collector contact region 203 may be applied to achieve punch through. For a 2 ohm-centimeter epitaxial layer, approximately 0.4 volts is required to punch through over 10 microns. With the various regions of the semiconductor device formed, an oxide layer 301, silicon dioxide for example, is present in the surface of the device as illustrated in FIG. 3F. Holes are made in the oxide layer for the later application of contacts to the various regions of the semiconductor device. With the higher concentration in base region 207, base stretching phenomonon is considerably reduced. Further, when impurities of a low coefficient of diffusion are employed to form buried region 207, side diffusion of buried region 201 during the epitaxial growth is reduced. These two factors, either individually or jointly, permit smaller transistor geometry and closer spacing of the devices, thus increasing the yield. Further advantages of the invention exist with respect to the structure of FIG. 1A. The prior art structure of FIG. 1A relies on outdiffusion during fabrication. Control of this outdiffusion process is not as exact as control of diffusion from the surface into the epitaxial layer. Further, outdiffusion during epitaxial growth in the prior art structure of FIG. 1A results in a wing formation which may be undesirable. For certain designs, particularly where a thicker epitaxial layer is desired in order to relax the required control of the epitaxial process, it may be advantageous to use a mixed impurity source of arsenic and phosphorus, for example, for the emitter and collector ring diffusions. In such cases, the phosphorus concentration is made lower than the base concentration but higher than the epitaxial layer impurity concentration. The emitter is formed substantially in the same way as if arsenic alone were present because the phosphorus does not penetrate beyond the arsenic in the base region due to the lower concentration of the phosphorus relative to the base impurity concentration. However, the phosphorus reaches deeper than the arsenic into the epitaxial layer to assure complete reach through to the buried collector region due to the higher concentration of the phosphorus than the epitaxial layer impurity concentration and the higher diffusion co-efficient of phosphorus relative to that of arsenic. It should also be noted, of course, that if another N diffusion step is to be used for the formation of a resistor, for example, in addition to the transistors of FIG. 2 in an integrated circuit device, the same resistor masking steps can be used to open the collector contact ring area 203 to enhance the reach through to buried collector region 201. It will be understood that the described process is applicable to a plurality of transistors and other devices being fabricatd simultaneously. For example, the processes and steps disclosed in this invention may be employed to fabricate pinch resistors. Also, while the invention has been described in terms of particular conductivity types, it is understood that the conductivity types May be reversed. In summary, the disclosed process results in a semiconductor structure in which high base concentrations are achievable without increasing the number of masked diffusion process steps necessary to fabricate existing structures of lower performance. Maintaining the number of masked diffusion steps at a minimum results in high yield. While the invention has been particulary shown and described with reference to the preferred embodiment thereof, it will be understood by those of skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. I claim: