Full capacity small size microprogrammed control unit

Claim 2

For use in a data processing system, a microprogram control unit comprising: an instruction storage for storing a plurality of words each containing a plurality of micro-order codes; instruction storage addressing means for addressing said instruction storage; instruction storage output means for holding a microinstruction which comprises micro-orders read from said instruction storage; a plurality of selectively operable gating means connected between said instruction storage and said instruction storage output means; an address storage for storing a plurality of words each containing the address of at least one word in said instruction storage and a configuration of mask bits representing the combination of micro-orders in said one word which comprise a desired microinstruction; address storage addressing means for addressing said address storage; address storage output means for holding data read from said address storage; means responsive to an address in said address storage addressing means to cause a word to be read from said address storage; means for causing an address read from said address storage to be transmitted to said instruction storage addressing means; means for causing a configuration of mask bits related to said last-named address to be transmitted to said address storage output means; means responsive to an address in said instruction storage addressing means to cause a word to be read from said instruction storage to said gating means; enabling means connected between said address storage output means and said gating means for enabling selected ones of said gating means in accordance with said configuration of mask bits; and means for causing micro-order codes which were read to gating means that were enabled by said enabling means to be transmitted to said instruction storage output means to form at least a portion of a microinstruction for controlling said data processing system.

Claim 3

The microprogram control unit of claim 1 further including: branch resolution means for determining addresses which are set into said address storage addressing Means; said branch resolution means having a first input connected to said address storage addressing means, a second input connected to another element of said data processing system for receiving status representation signals, and an output connected to said address storage addressing means for transmitting addresses thereto.

Claim 4

The microprogram control unit of claim 2 wherein: each of said plurality of words in said address storage contains a bit configuration representing at least one micro-order; said control unit further comprising means for causing a micro-order to be transmitted to said address storage output means when mask bits are transmitted thereto; and means for causing a micro-order to be transmitted from said address storage output means to said instruction storage output means to form another portion of said microinstruction for controlling said data processing system.

Claim 5

The microprogram control unit of claim 2 wherein said branch resolution means comprises: incrementing means for incrementing an address received from said address storage addressing means by a predetermined amount to form a tentative next address, said tentative next address being transmitted to said address storage addressing means; branch address generating means responsive to signals received at the inputs of said branch resolution means to generate an actual next address when said signals indicate that a microprogram branch is to be taken; and means for generating an output inhibit signal when a microprogram branch is to be taken, said inhibit signal being utilized to prevent the setting of an incorrect microinstruction into said instruction storage output means.

Claim 6

For use in a data processing system, a microprogram control unit comprising: an instruction storage for storing a plurality of words each containing a plurality of micro-order codes; instruction storage addressing means for addressing said instruction storage; instruction storage output means for holding a word read from said instruction storage; instruction register means for holding a microinstruction which comprises micro-orders read from said instruction storage; a plurality of selectively operable gating means connected between said instruction storage output means and said instruction register means; an address storage for storing a plurality of words each containing the address of at least one word in said instruction storage and a configuration of mask bits representing the combination of micro-orders in said one word which comprise a desired microinstruction; address storage addressing means for addressing said address storage; address storage output means for holding data read from said address storage; means responsive to an address in said address storage addressing means to cause a word to be read from said address storage; means for causing an address read from said address storage to be transmitted to said instruction storage addressing means; means for causing a configuration of mask bits related to said last-named address to be transmitted to said address storage output means; means responsive to an address in said instruction storage addressing means to cause a word to be read from said instruction storage to said instruction storage output means; means for transmitting said last named configuration of mask bits from said address storage output means to said instruction storage output means; enabling means connected between said instruction storage output means and said gating means for enabling selected ones of said gating means in accordance with said configuration of mask bits; and means for causing micro-order codes held in said instruction storage output means to be transmitted through the ones of said gating means that were enabled by said enabling means to said instruction register means to form at least a portion of a microinstruction for controlling said data processing system.

Claim 7

For use in a data processing system, a microprogram control unit comprising: an instruction storage for storing a plurality of words each containing a plurality of micro-order codes; instruction storage addressing means for addressing said instruction storage; instruction storage output means for holding a word read from said instruction storage; instruction register means for holding a microinstruction which comprises micro-orders read from said instruction storage; a plurality of selectively operable gating means connected between said instruction storage output means and said instruction register means; an address storage for storing a plurality of words each containing the address of at least one word in said instruction storage and a configuration of mask bits representing the combination of micro-orders in said one word which comprise a desired microinstruction; address storage addressing means for addressing said address storage; address storage output means for holding data read from said address storage; means responsive to an address in said address storage addressing means to cause a word to be read from said address storage; means for causing an address read from said address storage to be transmitted to said instruction storage addressing means; means for causing a configuration of mask bits related to said last-named address to be transmitted to said address storage output means; means responsive to an address in said instruction storage addressing means to cause a word to be read from said instruction storage to said instruction storage output means; means for transmitting said last named configuration of mask bits from said address storage output means to said instruction storage output means; enabling means connected between said instruction storage output means and said gating means for enabling selected ones of said gating means in accordance with said configuration of mask bits; and means for causing micro-order codes held in said instruction storage output means to be transmitted through the ones of said gating means that were enabled by said enabling means to said instruction register means to form at least a portion of a microinstruction for controlling said data processing system.

Claim 8

The microprogram control unit of claim 5 further including: branch resolution means for determining addresses which are set into said address storage addressing means; said branch resolution means having a first input connected to said address storage addressing means, a second input connected to another element of said data processing system for receiving status representation signals, and an output connected to said address storage addressing means for transmitting addresses thereto.

Claim 9

The microprogram control unit of claim 6 wherein: each of said plurality of words in said address storage contains a bit configuration representing at least one micro-order; said control unit further comprising means for causing a micro-order to be transmitted to said address storage output means when mask bits are transmitted thereto; and means for causing a micro-order to be transmitted from said address storage output means to said instruction storage output means and thence to said instruction register means to form another portion of said microinstruction for controlling said data processing system.

Claim 10

The microprogram control unit of claim 6 wherein said branch resolution means comprises: incrementing means for incrementing an address received from said address storage addressing means by a predetermined amount to form a tentative next address, said tentative next address being transmitted to said address storage addressing means; branch address generating means responsive to signals received at the inputs of said branch resolution means to generate an actual next address when said signals indicate that a microprogram branch is to be taken; and means for generating an output inhibit signal when a microprogram branch is to be taken, said inhibit signal being utilized to prevent the setting of an incorrect microinstruction into said instruction register means.