Patent US3786431A successfully refreshed from Google Patents.
US3786431A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic scanner checking process and system
Assignee: International Standard Electric Corp
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Filing: 1972-03-06
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Granted: 1974-01-15
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Expires: 1992-03-06
Abstract
Abstract An electronic scanner is started by a central processor to asynchronously scan a number of lines. When the scanner detects a calling line, it stops and calls the processor. The processor then starts the scanner again to operate till it detects another calling line or reaches the last line to be scanned. It is possible with such a system that the scanner will not operate properly and the central processor will not be informed of this fact. The invention provides for check scanning, without event detection, but with a stop at specified addresses.
Inventors
- 👤 C Bouchet
- 👤 V Ziliotto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:54
CPC Classifications
H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54575; H04Q3/54591; G; G06; G06F; G06F11/00; G06F11/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
149 words
A checking system for a scanner comprising register means for receiving and recording instruction signals and address signals from a central unit, order decoding means coupled to said register means responsive to instruction signals recorded in said register means to provide operate signals, first logic means responsive to a start order from a central unit to turn ''''on'''' and provide a GO signal, a clock coupled responsive to said GO signal to provide a plurality of time signals, gate means coupled to said register means to transmit address signals in synchronism with time signals from the clock, second logic means coupled to said register means to provide stop signals identify points to be tested in response to the address signals and to time signals from the clock, and third logic means responsive to the stop signals and to time signals to provide scan stop signals for stopping the system.
Claim 2
Dependent Claim
149 words
A checking system for a scanner comprising register means for receiving and recording instruction signals and address signals from a central unit, order decoding means coupled to said register means responsive to instruction signals recorded in said register means to provide operate signals, first logic means responsive to a start order from a central unit to turn ''''on'''' and provide a GO signal, a clock coupled responsive to said GO signal to provide a plurality of time signals, gate means coupled to said register means to transmit address signals in synchronism with time signals from the clock, second logic means coupled to said register means to provide stop signals identify points to be tested in response to the address signals and to time signals from the clock, and third logic means responsive to the stop signals and to time signals to provide scan stop signals for stopping the system.
Claim 3
Dependent Claim
44 words
The invention as claimed in claim 1, in which the register means includes a first portion to receive instruction signals and second and third portions to receive address signals, and said gate means is coupled to said second and third portions of the register.
Claim 4
Dependent Claim
29 words
The invention as claimed in claim 2, in which said second logic means is coupled to said third portion of the register to respond to address signals stored therein.
Claim 5
Dependent Claim
40 words
The invention as claimed in claim 1, in which the third logic means includes a plurality of gates adapted to respond to time signals from said clock and stop signals from said second logic means to provide scan stop signals.
Claim 6
Dependent Claim
37 words
The invention as claimed in claim 4, in which the first logic means includes a connection to receive scan stop signals causing said first logic means to turn ''''off'''' and provide a signal indicating the ''''off'''' stAtus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-14 | 1977-07-16 | 1978-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-14 | 1981-07-16 | 1982-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-14 | 1985-07-16 | 1986-01-15 | $7700.00 | Window Closed / Lapsed |