Adaptive delta modulation decoder

Claim 2

In a variable step size delta modulation system arranged to convert an analog signal to a stream of binary bits each occupying a given frame period, apparatus for reconverting said stream of binary bits to a replica of said analog signal, comprising, in combination, means for generating a current for a variable time interval during each of said frame periods, means for converting said current to a voltage proportional to the magnitude of the product of said current and said time interval, and means for adjusting the change in said voltage during each of said frame periods to correspond to the change in said analog signal during said frame peRiod, said last-named means comprising first means responsive to said stream of binary bits for varying said time interval in accordance with relatively short term changes in said analog signal, and second means responsive to said stream of binary bits for simultaneously varying the magnitude of said current in accordance with relatively long term changes in said analog signal envelope.

Claim 3

Apparatus in accordace with claim 1 wherein said first means comprises means for monitoring said stream of binary bits in order to provide an increase pulse in the presence of a first predetermined bit sequence and a decrease pulse in the presence of a second predetermined bit sequence, first counting means arranged to count up in response to said increase pulses and to count down in response to said decrease pulses, each of said counts being represented by an output terminal, means for dividing each of said frame periods into a plurality of equal time segments, and means for associating with each of said output terminals representing each of said counts a time interval measured by a predetermined number of said equal time segments.

Claim 4

Apparatus in accordance with claim 2 wherein said second means comprises an energy storage element for storing a control voltage, means for increasing said control voltage in response to said increase pulses and decreasing said control voltage in response to said decrease pulses, and means for modulating the magnitude of said current in proportion to said control voltage.

Claim 5

Apparatus in accordance with claim 2 wherein said means for monitoring said stream of binary bits includes a one bit memory arranged to compare each of said binary bits to the preceding one of said binary bits, said first predetermined bit sequence comprising successive bits of the same polarity, and said second predetermined bit sequence comprising successive bits of a different polarity.

Claim 6

Apparatus in accordance with claim 2 wherein said dividing means comprises means arranged to produce a plurality of timing pulses, and second counting means arranged to count said timing pulses during each of said frame periods, each of said counts being represented by an output terminal corresponding to an integral number of said equal time segments.

Claim 7

A variable step size delta modulation decoder comprising, in combination, first means for effecting instantaneous companding of said step sizes and second means for effecting syllabic companding of said step sizes, said first and said second means including means for enabling simultaneous operation thereof.

Claim 8

A variable step size delta modulation decoder comprising, in combination, first means for effecting instantaneous companding of said step sizes and second means for effecting syllabic companding of said step sizes, said first and said second means including means for enabling simultaneous operation thereof.

Claim 9

In an adaptive delta modulation system arranged to convert an analog signal to a stream of binary bits each of a given frame period, a decoder arranged to reconvert said stream of binary bits to a replica of said analog signal by periodically adjusting a stored voltage representative of said analog signal comprising, in combination, an energy storage element arranged to provide an output voltage change proportional to a time interval during which current is supplied thereto or extracted therefrom, and digital logic means for periodically controlling said output voltage change to correspond to changes in said analog signal, said last-named means comprising first means for monitoring said stream of binary bits arranged to provide an increase pulse in the presence of a series of bits in a first predetermined sequence indicative of an increasing slope of said analog signal and a decrease pulse in the presence of a series of bits in a second predetermined sequence indicative of a decreasing slope of said analog signal, second means, including a counter having a plurality of output terminals each of which represents a particular count thereof, arranged to count up in response to said increase pulses and to count down in response to said decrease pulses, third means for dividing each of said frame periods into a plurality of equal time segMents, fourth means jointly responsive to said second and third means for associating with each of said output terminals a particular number of said equal time segments, and means responsive to said last-named means for supplying a current to said energy storage element for a time interval during each of said frame periods determined by said particular number of time segments and of a polarity determined by said stream of binary bits.

Claim 10

In an adaptive delta modulation system arranged to convert an analog signal to a stream of binary bits each of a given frame period, a decoder arranged to reconvert said stream of binary bits to a replica of said analog signal by periodically adjusting a stored voltage representative of said analog signal comprising, in combination, an energy storage element arranged to provide an output voltage change proportional to a time interval during which current is supplied thereto or extracted therefrom, and digital logic means for periodically controlling said output voltage change to correspond to changes in said analog signal, said last-named means comprising first means for monitoring said stream of binary bits arranged to provide an increase pulse in the presence of a series of bits in a first predetermined sequence indicative of an increasing slope of said analog signal and a decrease pulse in the presence of a series of bits in a second predetermined sequence indicative of a decreasing slope of said analog signal, second means, including a counter having a plurality of output terminals each of which represents a particular count thereof, arranged to count up in response to said increase pulses and to count down in response to said decrease pulses, third means for dividing each of said frame periods into a plurality of equal time segMents, fourth means jointly responsive to said second and third means for associating with each of said output terminals a particular number of said equal time segments, and means responsive to said last-named means for supplying a current to said energy storage element for a time interval during each of said frame periods determined by said particular number of time segments and of a polarity determined by said stream of binary bits.

Claim 11

In a variable step size delta modulation system arranged to convert an analog signal to a stream of binary bits each occupying a given frame period, means for reconverting said stream of binary bits to said analog signal comprising first means arranged to monitor said stream of binary bits in order to provide an increase pulse in the presence of a first predetermined bit sequence and a decrease pulse in the presence of a second predetermined bit sequence, second means responsive to said first means arranged to increase said step sizes in response to said increase pulses and to decrease said step sizes in response to said decrease pulses, third means arranged to divide each of said frame periods into a plurality of equal time segments, fourth means arranged to associate with each of said step sizes a predetermined number of said time segments, an energy storage element, and fifth means arranged to supply current to said energy storage element of a polarity determined by said stream of binary bits, for a time interval determined by said number of time segments.

Claim 12

In a variable step size delta modulation system arranged to convert an analog signal to a stream of binary bits each occupying a given frame period, means for reconverting said stream of binary bits to said analog signal comprising first means arranged to monitor said stream of binary bits in order to provide an increase pulse in the presence of a first predetermined bit sequence and a decrease pulse in the presence of a second predetermined bit sequence, second means responsive to said first means arranged to increase said step sizes in response to said increase pulses and to decrease said step sizes in response to said decrease pulses, third means arranged to divide each of said frame periods into a plurality of equal time segments, fourth means arranged to associate with each of said step sizes a predetermined number of said time segments, an energy storage element, and fifth means arranged to supply current to said energy storage element of a polarity determined by said stream of binary bits, for a time interval determined by said number of time segments.

Claim 13

A variable step size delta modulation decoder for converting a binary bit stream to its analog signal equivalent comprising, capacitive means for storing a voltage representative of said analog signal, a current source connected to said capacitive means for effecting during a portion of each frame period of said binary bit stream a change in said stored voltage, and means responsive to said binary bit stream for controlling the magnitude of said voltage change, said last-named means comprising first means for varying said portion of each of said frame periods during which said current source is actuated, and second means for simultaneously varying the magnitude of the output of said current source.

Claim 14

A variable step size delta modulation decoder for converting a binary bit stream to its analog signal equivalent comprising, capacitive means for storing a voltage representative of said analog signal, a current source connected to said capacitive means for effecting during a portion of each frame period of said binary bit stream a change in said stored voltage, and means responsive to said binary bit stream for controlling the magnitude of said voltage change, said last-named means comprising first means for varying said portion of each of said frame periods during which said current source is actuated, and second means for simultaneously varying the magnitude of the output of said current source.

Claim 15

A variable step size delta modulation decoder for converting a binary bit stream to its analog signal equivalent, comprising, capacitive means for storing a voltage representative of said analog signal, a controllable source of current for periodically changing said stored voltage in accordance with a variable step size, and means responsive to said binary bit stream for periodically varying the magnitude of said step sizes, said last-named means comprising first means for effecting instantaneous companding of said step sizes in combination with second means for simultaneously effecting syllabic companding of said step sizes.

Claim 16

A variable step size delta modulation decoder for converting a binary bit stream to its analog signal equivalent, comprising, capacitive means for storing a voltage representative of said analog signal, a controllable source of current for periodically changing said stored voltage in accordance with a variable step size, and means responsive to said binary bit stream for periodically varying the magnitude of said step sizes, said last-named means comprising first means for effecting instantaneous companding of said step sizes in combination with second means for simultaneously effecting syllabic companding of said step sizes.

Claim 17

A decoder for the conversion of a stream of binary bits each of a given frame period to an analog signal representation thereof comprising, in combination, a capacitive element for storing a voltage representative of said analog signal, a memory device for periodically comparing each bit of said bit stream with a predetermined number of previous bits, thereby producing an indication of the magnitude of a deviation of said analog signal from its instantaneous value stored on said capacitive element, a first counter responsive to said memory device having a plurality of output terminals each corresponding to a respective one of the possible counts thereof and representative of the relative magnitude of said deviation, a high speed timer having a frequency m times greater than that of said binary bit stream for dividing each of said frame periods into m equal time segments, a second counter responsive to said high speed timer having a plurality of output terminals each corresponding to an integral multiple of said equal time segments, coincidence logic for associating with each of said possible counts of said first counter a time interval measured by a predetermined number of said equal time segments, and a current source responsive to said coincidence logic for charging or discharging said capacitive element during said time interval.

Claim 18

A decoder for the conversion of a stream of binary bits each of a given frame period to an analog signal representation thereof comprising, in combination, a capacitive element for storing a voltage representative of said analog signal, a memory device for periodically comparing each bit of said bit stream with a predetermined number of previous bits, thereby producing an indication of the magnitude of a deviation of said analog signal from its instantaneous value stored on said capacitive element, a first counter responsive to said memory device having a plurality of output terminals each corresponding to a respective one of the possible counts thereof and representative of the relative magnitude of said deviation, a high speed timer having a frequency m times greater than that of said binary bit stream for dividing each of said frame periods into m equal time segments, a second counter responsive to said high speed timer having a plurality of output terminals each corresponding to an integral multiple of said equal time segments, coincidence logic for associating with each of said possible counts of said first counter a time interval measured by a predetermined number of said equal time segments, and a current source responsive to said coincidence logic for charging or discharging said capacitive element during said time interval.