US3784919A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Drift-compensated analog hold circuit
Assignee: Fischer and Porter Co
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Filing: 1972-08-14
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Granted: 1974-01-08
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Expires: 1992-08-14
Abstract
Abstract A drift-compensated analog hold circuit in which the output of the analog hold circuit is converted into a pulse train signal which is compared with reference clock pulses to detect the amount of drift in terms of a time-based signal. An analog drive circuit responsive to this time-based signal supplies a drift compensation signal to the analog hold circuit.
Inventors
- 👤 T Azegami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:46
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
159 words
A drift-compensated analog hold circuit comprising: a. an analog hold circuit composed of an amplifier and an integrating capacitor, b. a converter circuit connected to the output of the analog hold circuit to convert the output of said analog hold circuit to a pulse train signal having a frequency which has a predetermined functional relationship to the output voltage of said analog hold circuit, c. a clock pulse generator yielding a clock pulse signal having a definite frequency, d. an And-gate having one input coupled to said converter circuit for receiving said pulse signal and having another input connected to said generator for receiving said clock pulse signal, said And-gate yielding an output signal when said two signals overlap, and e. an analog drive circuit connected between the output of said And-gate and the input of said amplifier for delivering a compensation signal to the input of said amplifier when the output signal of said And-gate is fed thereto.
Claim 2
Dependent Claim
159 words
A drift-compensated analog hold circuit comprising: a. an analog hold circuit composed of an amplifier and an integrating capacitor, b. a converter circuit connected to the output of the analog hold circuit to convert the output of said analog hold circuit to a pulse train signal having a frequency which has a predetermined functional relationship to the output voltage of said analog hold circuit, c. a clock pulse generator yielding a clock pulse signal having a definite frequency, d. an And-gate having one input coupled to said converter circuit for receiving said pulse signal and having another input connected to said generator for receiving said clock pulse signal, said And-gate yielding an output signal when said two signals overlap, and e. an analog drive circuit connected between the output of said And-gate and the input of said amplifier for delivering a compensation signal to the input of said amplifier when the output signal of said And-gate is fed thereto.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-07 | 1977-07-09 | 1978-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-07 | 1981-07-09 | 1982-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-07 | 1985-07-09 | 1986-01-08 | $7700.00 | Window Closed / Lapsed |