Patent US3384155A successfully refreshed from Google Patents.
US3784918A
Expired / Lapsed
US
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Storage circuits
Assignee: RCA Corp
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Filing: 1972-10-20
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Granted: 1974-01-08
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Expires: 1992-10-20
Abstract
Abstract Each stage of a register includes first and second logical product gates, a logical sum gate receptive of the signals produced by the logical product gates and a feedback connection from the logical sum gate to the second logical product gate. A data signal is applied to the first logical product gate. In response to one binary value of a timing pulse, the first logical product gate is primed and the second disabled and in response to the other binary value of the timing pulse, the first logical product gate is disabled and the other primed.
Inventors
- 👤 C Fassbender
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
230 words
A register comprising, in combination: a a plurality of register stages, each such stage comprising: first and second logical product gates; a logical sum gate connected to receive the signals produced by said first and second gates and supplying its output signal to said second gate; and an input lead for a data signal connected to said first gate; and a control circuit common to all of said register stages, said control circuit comprising first control gate means responsive to a timing signal for applying a disabling signal to all of said second gates when said timing signal has one binary value and for applying a priming signal to all of said second gates when said timing signal has the other binary value, and for producing also a second signal having one binary value when said timing signal has said one binary value and a second binary value when said timing signal has the other binary value, and second control gate means responsive to a control signal and to said second signal for applying a priming signal to the first gate of all of said stages when said control signal and said one binary value of second signal are present and for applying a disabling signal to the first gate of all of said stages when either the control signal or said one binary valve of second signal is absent.
Claim 2
Dependent Claim
230 words
A register comprising, in combination: a a plurality of register stages, each such stage comprising: first and second logical product gates; a logical sum gate connected to receive the signals produced by said first and second gates and supplying its output signal to said second gate; and an input lead for a data signal connected to said first gate; and a control circuit common to all of said register stages, said control circuit comprising first control gate means responsive to a timing signal for applying a disabling signal to all of said second gates when said timing signal has one binary value and for applying a priming signal to all of said second gates when said timing signal has the other binary value, and for producing also a second signal having one binary value when said timing signal has said one binary value and a second binary value when said timing signal has the other binary value, and second control gate means responsive to a control signal and to said second signal for applying a priming signal to the first gate of all of said stages when said control signal and said one binary value of second signal are present and for applying a disabling signal to the first gate of all of said stages when either the control signal or said one binary valve of second signal is absent.
Claim 3
Dependent Claim
19 words
A register as set forth in claim 1, wherein said second control gate means comprises a single AND gate.
Claim 4
Dependent Claim
72 words
A regiser as set forth in claim 1, wherein said control signal comprises said timing signal, and wherein said second control gate means comprises a first non-inverting gate receptive of said second signal, a second non-inverting gate receptive of said timing signal, and a logical sum gate connected to receive the outputs of said first and second non-inverting gates and supplying its output to the first gate of all of said stages.
Claim 5
Dependent Claim
66 words
A register as set forth in claim 1, wherein each first gate and the logical sum gate connected thereto together introduce a total delay of one stage delay, each second gate and the logical sum gate connected thereto together introduce a total delay of one stage delay, said first control gate means introduces one stage delay, and said second control gate means introduces one stage delay.
Claim 6
Dependent Claim
89 words
A register as set forth in claim 1 wherein each stage includes a third logical product gate, and an input lead for A second data signal connected to that gate, and supplying its output to the logical sum gate for that stage, and wherein said control circuit includes another control gate means receptive of another control signal and of said second signal for applying a priming signal the third logical product gate of all stages when said another control signal and said one value of second signal are present.
Claim 7
Dependent Claim
35 words
A register as set forth in claim 1, wherein said first gate means of said control circuit comprises a gate for producing said second signal and its complement, said complementary signal comprising said disabling signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-07 | 1977-07-09 | 1978-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-07 | 1981-07-09 | 1982-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-07 | 1985-07-09 | 1986-01-08 | $7700.00 | Window Closed / Lapsed |