One-out-of-n storage circuit employing at least 2n gates for n input signals

Claim 1

IN COMBINATION, N PAIRS OF GATES, EACH GATE OF THE TYPE WHICH BECOMES DISABLED WHEN ONE OR MORE INPUT SIGNALS TO THE GATE IS IN A SENSE TO DISABLE THE GATE, EACH PAIR OF GATES COMPRISING A FIRST GATE AND A SECOND GATE, WHERE N IS AN INTEGER; MEANS FOR APPLYING TO EACH FIRST GATE A DIFFERENT ONE OF N SIGNALS, ONE OF SAID N SIGNALS REPRESENTING A BIT OF ONE VALUE AND BEING OF A SENSE TO PRIME THE GATE TO WHICH IT IS APPLIED, AND ALL OTHER OF SAID N SIGNALS REPRESENTING THE BIT OF OTHER VALUE AND BEING OF A SENSE TO DISABLE THE GATES TO WHICH THEY ARE APPLIED; MEANS FOR APPLYING A TIMING SIGNAL TO ALL FIRST GATES FOR ENABLING THE ONE OF THE FIRST GATES WHICH RECEIVES THE SIGNAL INDICATIVE OF SAID BIT OF ONE VALUE; MEANS FOR PRODUCING N SIGNALS INDICATIVE OF THE LOGICAL SUMS OF THE OUTPUTS OF SAID N PAIRS OF GATES, RESPECTIVELY; AND MEANS FOR APPLYING EACH SIGNAL INDICATIVE OF THE LOGICAL SUM OF THE OUTPUTS OF EACH PAIR OF GATES TO THE SECOND GATES OF ALL OTHER PAIRS OF GATES, IN A SENSE TO ENABLE THE SECOND GATE ASSOCIATED WITH THE ENABLED FIRST GATE, AND IN A SENSE TO DISABLE THE REMAINING N-1 SECOND GATES.