Multi-mode computing circuit

Claim 2

A multi-mode computing circuit capable of calculating an output voltage VO as a function of three variable input voltages, VA, VB, and VC, according to the general formula, VO VA(VC/VB)n, where VC is greater than VB and n is a determinable value of the circuit, comprising: first aNd second relaxation oscillator means; energizing means for simultaneously charging said first oscillator means with VC and said second oscillator means with VO for a finite time period and for permitting decay of both of said oscillator means after said time period expires; first comparator means for comparing the voltage in said first oscillator means with VB and for sensing the response time of said first oscillator means during decay; second comparator means for comparing the voltage in said second oscillator means with VA and for sensing the response time of said second oscillator means during decay; correction means controlled by the voltages compared at said first and second comparator means for adjusting the value of VO and for urging the difference of said response times to decrease; and sequencing means operated by said first and second comparator means for successively activating said energizing means after VO has been adjusted to cause VO to be readjusted and to calculate VO VA (VC/VB)n when said response times are equal.

Claim 3

The circuit of claim 1 wherein said energizing means permits simultaneous decay of both of said oscillator means.

Claim 4

The circuit of claim 1 wherein said energizing means is adjustable to permit said finite time period to be varied.

Claim 5

The circuit of claim 2 wherein said first oscillator means includes a RC circuit having a resistor R1 arranged in parallel with a capacitor C1.

Claim 6

The circuit of claim 4 wherein said second oscillator means is a RC circuit having a resistor R2 arranged in parallel with a capacitor C2.

Claim 7

The circuit of claim 5 wherein n R1C1/R2C2.

Claim 8

The circuit of claim 6 wherein R1 is an adjustable resistor for permitting n to be varied.

Claim 9

The circuit of claim 1 wherein said first comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said first oscillator means is greater than VB, a negative signal when such voltage is less than VB, and a null signal when such voltage is equal to VB.

Claim 10

The circuit of claim 1 wherein said second oscillator means is a voltage comparator capable of generating a positive output signal when the voltage in said second oscillator means is greater than VA, a negative signal when such voltage is less than VA, and a null signal when such voltage is equal to VA.

Claim 11

The circuit of claim 3 wherein said energizing means includes first electronic switch means between VC and said first oscillator means, second electronic switch means between VO and said second oscillator means, and a monostable multivibrator operatively associated with said first and second electronic switch means to close said switch means when said multivibrator is excited into its quasi-stable state and to open said switches when said multivibrator reverts to its stable state.

Claim 12

The circuit of claim 10 wherein said monostable multivibrator is adjustable to vary said finite time period.

Claim 13

The circuit of claim 1 wherein said sequencing means includes an AND gate.

Claim 14

The circuit of claim 1 wherein said correction means includes a voltage supply circuit operated by said second comparator means to increase VO when said response time of said second oscillator means is less than said response time of said first oscillator means.

Claim 15

The circuit of claim 13 wherein said correction means further includes a voltage drain circuit operated by said first comparator means to decrease VO when said response time of said first oscillator means is less than said response time of said second oscillator means.

Claim 16

The circuit of claim 14 wherein said correction means further includes capacitor arranged in parallel with said voltage drain circuit.

Claim 17

The circuit of claim 15 further comprising a buffer amplifier between said correction means and said second comparator means.

Claim 18

A multi-mode computing circuit capable of calculating an output voltage VO as a function of two variable input voltages, VB and VC, according to the general formula, VO K 1n (VC/VB)T , where VC is greater than VB and where C and T1 are determinable values of the circuit comprising: relaxation oscillator means; a source of constant current; capacitor means supplied with said constant current; energizing means for simultaneously charging said oscillator means with VC and for draining said capacitor means for a finite time period and for permitting said oscillator means to decay and said capacitor means to charge after said time period expires; first comparator means for comparing the voltage in said oscillator means with VB and for sensing the response time of said oscillator means during decay; second comparator means for comparing the voltage in said capacitor means with VO and for sensing the response time of such capacitor means during charging; correction means controlled by the relative voltages compared at said first and second comparator means to adjust VO for urging the difference between said oscillator response time and said charging capacitor means response time to decrease; and sequencing means for successively activating said energizing means after VO has been adjusted to cause VO to be readjusted and to calculate VO K 1n(VC/VB)T when said response times are equal.

Claim 19

A multi-mode computing circuit capable of calculating an output voltage VO as a function of two variable input voltages, VB and VC, according to the general formula, VO K 1n (VC/VB)T , where VC is greater than VB and where C and T1 are determinable values of the circuit comprising: relaxation oscillator means; a source of constant current; capacitor means supplied with said constant current; energizing means for simultaneously charging said oscillator means with VC and for draining said capacitor means for a finite time period and for permitting said oscillator means to decay and said capacitor means to charge after said time period expires; first comparator means for comparing the voltage in said oscillator means with VB and for sensing the response time of said oscillator means during decay; second comparator means for comparing the voltage in said capacitor means with VO and for sensing the response time of such capacitor means during charging; correction means controlled by the relative voltages compared at said first and second comparator means to adjust VO for urging the difference between said oscillator response time and said charging capacitor means response time to decrease; and sequencing means for successively activating said energizing means after VO has been adjusted to cause VO to be readjusted and to calculate VO K 1n(VC/VB)T when said response times are equal.

Claim 20

The circuit of claim 17 wherein said energizing means simultaneously permits said capacitor means to charge and said oscillator means begins to decay.

Claim 21

The circuit of claim 18 wherein said oscillator means includes an RC circuit having a resistor R1 arranged in parallel with a capacitor C1.

Claim 22

The circuit of claim 19 wherein T1 R1C1.

Claim 23

The circuit of claim 20 wherein R1 is an adjustable resistor for permitting T1 to be varied.

Claim 24

The circuit of claim 17 wherein said energizing means is adjustable to permit said finite time period to be varied.

Claim 25

The circuit of claim 22 wherein said first comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said oscillator means is greater than VB, a negative signal when such voltage is less than VB, and a null signal when such voltage is equal to VB.

Claim 26

The circuit of claim 18 wherein said second comparator means is a voltage comparator capable of generating a positive output signal when the voltage in said capacitor means is greater than V0, a negative signal when such voltage is less than VO, and a null signal when such voltage is equal to VO.

Claim 27

The circuit of claim 22 wherein said energizing means includes first electronic switch means between VC and said oscillator means, third electronic switch means arranged in parallel with said capacitor means, and a monostable multivibrator operatively associated with said first and third electronic switch means to close said switch means when said multivibrator is excited into its quasi-stable state and to open said switch means when said multivibrator reverts to its stable state.

Claim 28

The circuit of claim 25 wherein said monostable multivibrator is adjustable to vary said finite time period.

Claim 29

The circuit of claim 18 wherein said sequencing means includes an AND gate.

Claim 30

The circuit of claim 18 wherein said correction means includes a voltage supply circuit operated by said second comparator means to increase VO when said response time of said capacitor means during charging is less than said response time of said oscillator means during decay.

Claim 31

The circuit of claim 28 wherein said correction means further includes a voltage drain circuit operated by said first comparator means to decrease VO when said response time of said oscillator means during decay is less than said response time of said capacitor means during charging.

Claim 32

The circuit of claim 29 wherein said correction means further includes a capacitor arranged in parallel with said voltage drain circuit.

Claim 33

The circuit of claim 30 further comprising a buffer amplifier between said correction means and said second comparator means.

Claim 34

The circuit of claim 17 wherein said capacitor means is a capacitor.