Digital diversity combiner

Claim 2

A predetection maximal ratio digital diversity combiner for a phase shift keyed digital data signal propagating on N different paths through a dispersive medium,where N is an integer greater than one, comprising: N signal channels, each of said channels responding to said data signal propagating on a different one of said N different paths; each of said channels including first means to separate said data signal into an inphase component and a quadrature component, and second means coupled to said first means to convert said inphase component into an inphase digital signal and said quadrature component into a quadrature digital signal; third means coupled in common to the output of each of said channels to digitally add said inphase digital signal of each of said channels together to produce a combined inphase digital signal and to digitally add said quadrature digital signal of each of said channels together to produce a combined quadrature digital signal; fourth means coupled to said third means responsive to said combined inphase digital signal and said combined quadrature digital signal to recover the data conveyed by said data signal; each of said channels further including fifth means coupled between said second means and said third means and to said fourth means responsive to said recovered data to weight said inphase digital signal and said quadrature digital signal prior to digitally adDing thereof in said third means; and sixth means coupled to said fifth means of each of said channels to produce an automatic gain control signal for control of the gain of said data signal in each of said channels.

Claim 3

A combiner according to claim 1, wherein said N different paths are provided by a space diversity system.

Claim 4

A combiner according to claim 1, wherein said N different paths are provided by an angle diversity system.

Claim 5

A combiner according to claim 1, wherein data conveyed by said data signal includes a 90* carrier phase increase for each binary ''''1'''' data bit, and a 90* carrier phase decrease for each binary ''''0'''' data bit.

Claim 6

A combiner according to claim 1, wherein said data signal propagating on said N different paths includes a carrier having a given RF frequency; and each of said N channels further including a down converter coupled between the associated one of said N different paths and the associated one of said first means to convert said carrier having a given RF frequency to a carrier having a given IF frequency.

Claim 7

A combiner according to claim 1, wherein each of said first means includes a first balanced mixer coupled to the associated one of said N different paths, a second balanced mixer coupled to said associated one of said N different paths, an oscillator having a frequency equal to the carrier frequency of said data signal, said oscillator being directly connected to said first mixer, and a 90* phase shifter coupled between said oscillator and said second mixer, said first mixer producing said inphase component and said second mixer producing said quadrature component.

Claim 8

A combiner according to claim 1, wherein each of said second means includes a first analog-to-digital converter coupled to said first means responsive to said inphase component to produce said inphase digital signal, and a second analog-to-digital converter coupled to said first means responsive to said quadrature component to produce said quadrature digital signal.

Claim 9

A combiner according to claim 1, wherein said third means includes a first digital adder arrangement coupled to said output of each of said channels to produce said combined inphase digital signal, and a second digital adder arrangement coupled to said output of each of said channels to produce said combined quadrature digital signal.

Claim 10

A combiner according to claim 8, wherein N is equal to an even integer, said first digital adder arrangement includes a first tier of digital adders to add said inphase digital signals of each of said channels in pairs, a second tier of digital adders coupled to said first tier of digital adders to add the resultant output signals of each of said first tier of digital adders in pairs, and additional tiers of digital adders coupled to the preceding tier of digital adders to add the resultant output signals of each of said preceding tier of digital adders until said combined inphase digital signal is produced, and said second digital adder arrangement includes a plurality of tiers of digital adders arranged and functioning identical to said first, second and additional tiers of digital adders but operating on said quadrature digital signal to produce said combined quadrature digital signal.

Claim 11

A combiner according to claim 1, wherein said fourth means includes a digital decision circuit coupled to said third means responsive to the most significant bit of both said combined inphase digital signal and said combined quadrature digital signal to recover said data conveyed by said data signal, and a digital clock recovery circuit coupled to said third means and said decision circuit responsive to said combined inphase digital signal, said combined quadrature digital signal and said recovered data to generate a bit rate clock in pHase with the bit rate of said data signal and to produce a plurality of timing signals to control the operation of said decision circuit,each of said second means and each of said fifth means.

Claim 12

A combiner according to claim 1, wherein each of said fifth means include first logic circuitry coupled to said fourth means and said second means responsive to said inphase and quadrature digital signals and said recovered data to compensate for carrier phase shift in said inphase and quadrature digital signals, second logic circuitry coupled to said first logic circuitry responsive to said compensated inphase and quadrature digital signals to determine the maximal ratio weights of said inphase and quadrature digital signals, and third logic circuitry coupled to said second means and said second logic circuitry to weight said inphase and quadrature digital signals according to said determined maximal ratio weights.

Claim 13

A combiner according to claim 11, wherein said second logic circuitry includes a first digital averaging circuit coupled to said first logic circuitry to digitally average said compensated inphase digital signal to determine the maximal ratio weight of said inphase digital signal and to produce a first digital weight signal representing said determined maximal ratio weight of said inphase digital signal, and a second digital averaging circuit coupled to said first logic circuitry to digitally average said compensated quadrature digital signal to determine the maximal ratio weights of said quadrature digital signal and to produce a second digital weight signal representing said determined maximal weight of said quadrature digital signal.

Claim 14

A combiner according to claim 12, wherein said third logic circuitry includes a first digital arrangement coupled to said second means and said first and second averaging circuits to multiply each bit of said inphase and quadrature digital signals with each bit of said first and second digital weight signals according to a first predetermined pattern and to produce therefrom said weighted inphase digital signal,and a second digital arrangement coupled to said second means and said first and second averaging circuits to multiply each bit of said inphase and quadrature digital signals with each bit of said first and second digital weight signal according to a second predetermined pattern different than said first pattern and to produce therefrom said weighted quadrature digital signal.

Claim 15

A combiner according to claim 12, wherein said sixth means includes seventh means coupled to said first and second averaging circuit of each of said N channels to determine which of said channels contains the maximum of said weight signals, and eighth means coupled to said seventh means to produce an automatic gain control voltage from said determined maximum weight signals.

Claim 16

A combiner according to claim 14, wherein said seventh means includes a digital selector means coupled to said first and second averaging circuit of each of said N channels to select sequentially one of said first and second weight signals of each of said N channels, a digital register to store the previous maximum one of said first and second weight signals of one of said N channels, and a digital comparator coupled to the output of said selector means, the output of said register and the input of said register to compare the present selected one of said first and second weight signals of one of said N channels with that one of said first and second weight signals of one of said N channels stored in said register and to couple the maximum one of said compared weight signals to the input of said register and to said eighth means.

Claim 17

A combiner according to claim 15, wherein said eighth means includes a digital-to-analog converter coupled to said comparator to convert said maximum one of said compared weight signals to an automatic gain control voltage. 17. A combiner according to claim 1, wherein said data signal propagating on said N different paths including a carrier having a given RF frequency; each of said N channels further includes a down converter coupled between the associated one of said N different paths and the associated one of said first means to convert said carrier having a given RF frequency to a carrier having a given IF frequency; each of said first means includes a bandpass filter coupled to the associated one of said down converters, an IF amplifier coupled to said band pass filter, a first balanced mixer coupled to said IF amplifier, a second balanced mixer coupled to said IF amplifier, an oscillator having a frequency equal to said given IF frequency, said oscillator being directly connected to said first mixer, and a 90* phase shifter coupled between said oscillator and said second mixer, said first mixer producing said inphase component and said second mixer producing said quadrature component; each of said second means includes a first low pass filter coupled to the associated one of said first mixers, a second low pass filter coupled to the associated one of said second mixers, a first analog-to-digital converter coupled to said first low pass filter responsive to said inphase component to produce said inphase digital signal, and a second analog-to-digital converter coupled to said second low pass filter responsive to said quadrature component to produce said quadrature digital signal; said third means includes a first digital adder arrangement coupled to said output of each of said channels to produce said combined inphase digital signal, and a second digital adder arrangement coupled to said output of each of said channels to produce said combined quadrature digital signal; said fourth means includes a digital decision circuit coupled to said first and second digital adder arrangements responsive to the most significant bit of both of said combined inphase digital signal and said combined quadrature digital signal to recover said data conveyed by said data signal, and a digital clock recovery circuit coupled to said first and second digital adder arrangements and said decision circuit responsive to said combined inphase digital signal, said combined quadrature digital signal and said recovered data to generate a bit rate clock in phase with the bit rate of said data signal and to produce a plurality of timing signals to control the operation of said decision circuit , each of said first analog-to-digital converters, each of said second analog-to-digital converters and each of said fifth means; each of said fifth means include first logic circuitry coupled to said decision circuit and the associated one of said analog-to-digital converters responsive to said inphase and quadrature digital signals and said recovered data to compensate for carrier phase shift in said inphase and quadrature digital signals, second logic circuitry coupled to said first logic circuitry responsive to said compensated inphase and quadrature digital signals to determine the maximal ratio weights of said inphase and quadrature digital signals, and third logic circuitry coupled to said associated one of said first and second analog-to-digital converters and said second logic circuitry to weight said inphase and quadrature digital signals according to said determined maximal ratio weights; and said sixth means includes seventh means coupled to said second logic circuitry of each of said N channels to determine which of said channels contains the maximum of said determined maximal ratio weights,and eighth means coupled to said seventh means to produce an automatic gain control voltage from said maximum determined maximal ratio weights for coupling to each of said IF amplifier.