Patent US3781827A successfully refreshed from Google Patents.
US3781827A
Expired / Lapsed
US
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Device for storing information and providing an electric readout
Assignee: General Electric Co
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Filing: 1971-11-24
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Granted: 1973-12-25
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Expires: 1991-11-24
Abstract
Abstract An information storing method and a storing device using a conductor-insulator-semiconductor (CIS) structure as the storage element is disclosed within. The CIS structure is initially charged to a predetermined voltage, forming a depletion region within the semiconductor beneath the conductor. Minority carriers are controllably generated within the semiconductor in proportional response to an information-bearing signal such as a specific amount of electromagnetic radiation flux. The generated minority carriers move to and are stored at the surface of the semiconductor beneath the conductor due to the electric field existing in the depletion region, thus changing the predetermined voltage. The change in voltage which may be determined in a measure of the number of generated minority carriers and, therefore, is a measure of the integrated electromagnetic radiation flux and constitutes the stored information.
Inventors
- 👤 W Engeler
- 👤 M Garfinkel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:21
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/35; G11C13/00; G11C13/04; G11C13/048; H; H10; H10D; H10D99/00; H10F; H10F30/00; H10F30/20; H10F30/21; H10F30/28; H10F30/2823; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H10B; H10B99/00; H10B99/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
123 words
Information storage and readout apparatus comprising a. a plurality of discrete semiconductor capacitive elements closely positioned in a matrix having a predetermined pattern, each capacitive element adapted to exist in a first voltage condition and in a second voltage condition; b. means for individually addressing each capacitive element; set-reset means associated with each of said capacitive elements for establishing said first voltage condition; c. output means associated with each of said semiconductor capacitive elements for conducting an output current substantially corresponding to a change of the initially predetermined voltage caused by the presence of minority carrier generated within said semiconductor capacitive element; and d. wherein said set-reset means and said output means are operative only when a selective capacitive element is being addressed.
Claim 2
Dependent Claim
123 words
Information storage and readout apparatus comprising a. a plurality of discrete semiconductor capacitive elements closely positioned in a matrix having a predetermined pattern, each capacitive element adapted to exist in a first voltage condition and in a second voltage condition; b. means for individually addressing each capacitive element; set-reset means associated with each of said capacitive elements for establishing said first voltage condition; c. output means associated with each of said semiconductor capacitive elements for conducting an output current substantially corresponding to a change of the initially predetermined voltage caused by the presence of minority carrier generated within said semiconductor capacitive element; and d. wherein said set-reset means and said output means are operative only when a selective capacitive element is being addressed.
Claim 3
Dependent Claim
17 words
The apparatus of claim 1 wherein each of said discrete capacitive elements is a p-n junction device.
Claim 4
Dependent Claim
51 words
Information storage and readout apparatus of claim 1 wherein the discrete capacitive elements each include: a. a semiconductor member; b. an insulator member on one major surface of said semiconductor member; and c. a conductor member on the surface of said semiconductor member for charging said capacitor to a predetermined voltage.
Claim 5
Dependent Claim
28 words
The apparatus of claim 3 including a substrate of semiconductor material wherein said semiconductor member of each capacitive element comprises a portion of said substrate of semiconductor material.
Claim 6
Dependent Claim
13 words
The apparatus of claim 4 wherein said substrate of semiconductor material is silicon.
Claim 7
Dependent Claim
70 words
The apparatus of claim 4 wherein said capacitive elements are arranged in an array of rows and columns and said set-reset means sequentially charges an entire row of said capacitive elements at substantially the same time when said entire row is being addressed by said addressing means and sequentially discharges each capacitor of a row of said capacitive elements as each capacitive element is being addressed by said addressing means.
Claim 8
Dependent Claim
134 words
The apparatus of claim 6 in which said addressing means comprises a set-reset control device for each capacitive element, an output control device associated with each capacitor, and an addressing line for each row and column; said set-reset means comprises a plurality of set-reset lines each associated with a column; said output means comprises a plurality of output lines each associated with a column; a. wherein said set-reset control device electrically connects the associated capacitive element to the associated set-reset line when the associated row and column addressing lines are simultaneously on; and b. wherein said output control device is electrically connected to an associated output line and produces the output current when said associated row and column addressing lines are simultaneously on and said associated set-reset line is discharging the associated capacitive element.
Claim 9
Dependent Claim
98 words
The apparatus of claim 7 wherein said set-reset control device is a multigate field effect transistor having the source connected to the associated set-reset line and drain to the associated capacitive element and wherein said gates are connected respectively to the associated address row line and associated address column line and a. wherein said output control means is a multigate field effect transistor in which the gates are respectively connected to the associated address row line and associated address column line, the drain is connected to the associated output line, and the source is connected to said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |