Digital phase-locked-loop

Claim 2

A digital phase-locked-loop circuit for locking in phase a first signal and a second signal of substantially the same frequency comprising in combination: bistable means having an up-enable and a down-enable output and responsive to certain phase angles of said first signal to set said bistable means to said up-enable output and responsive to the same phase angles of said second signal to reset said bistable means to said down-enable output; oscillator means for producing a reference signal having a frequency fr; counter means operably connected to said bistable means and said oscillator means for counting in one direction in response to said up-enable output and for counting in the opposite direction in response to said down-enable output at some counting rate proportional to the frequency of said reference signal to provide a resultant count output; and divider means operably connected to said oscillator means and said counter means having an output of said second signal.

Claim 3

The digital phase-locked-loop circuit of claim 1 wherein said phase-locked-loop further includes comparator means responsive to said first signal for deriving a series of pulses coincident with the zero crossing points of said first signal, said series of pulses applied to said bistable means to set said bistable means to said up-enable output.

Claim 4

The digital phase-locked-loop circuit of claim 1 wherein said counter means includes an up-down counter having k stages for providing a count signal directly proportional to both the frequency of said reference signal and the phase difference of said first and second signals and inversely proportional to the factor 2k.

Claim 5

The digital phase-locked-loop circuit of claim 3 wherein said divider means is a divide-by-K circuit, and further wherein the frequency of said reference signal is greater by said factor K than the frequency of said first signal.

Claim 6

The digital phase-locked-loop circuit of claim 4 wherein said phase-locked-loop has a closed loop transfer function H(s) a/s+a where the loop gain a 2fr/K2k.

Claim 7

The digital phase-locked-loop circuit of claim 4 wherein said divide-by-K circuit has an output frequency Fo fr/K (1 -(1/2k)) when the phase difference between said first signal and said second signal is - pi radians and has an output frequency fo (fr/K) (1 + (1/2k)) when the phase difference between said first signal and said second signal is pi radians and has some intermediate output frequency for phase differences between - pi radians and + pi radians.

Claim 8

A digital phase-locked-loop for looking in phase a first signal and a second signal of substantially the same frequency comprising: means for producing a reference signal at a frequency fr; gain means operably responsive to said reference signal and to said first and second signals for comparing the phase of said first signal with the phase of said second signal to obtain a resultant count signal linearly proportional to the phase difference between said first and said second signals; divider means having an output of said second signal operably connected to said gain means responsive to said resultant count signal and said reference signal for shifting the phase of said second signal to lock in phase with said first signal.

Claim 9

A digital phase-locked-loop for looking in phase a first signal and a second signal of substantially the same frequency comprising: means for producing a reference signal at a frequency fr; gain means operably responsive to said reference signal and to said first and second signals for comparing the phase of said first signal with the phase of said second signal to obtain a resultant count signal linearly proportional to the phase difference between said first and said second signals; divider means having an output of said second signal operably connected to said gain means responsive to said resultant count signal and said reference signal for shifting the phase of said second signal to lock in phase with said first signal.

Claim 10

A digital phase-locked-loop system for locking in phase a plurality of pairs of first and second signals each pair of substantially the same frequency comprising in combination: a plurality of phase-locked-loops each including, bistable means having an up-enable and a down-enable output responsive to certain phase angles of a first signal to set said bistable means to said up-enable output and responsive to the same phase angles of a second signal to reset said bistable means to said down-enable output; oscillator means for producing a reference signal having a frequency fr; counter means operably connected to said bistable means and said oscillator means for counting in one direction in response to said up-enable output and for counting in the opposite direction in response to said down-enable output at some counting rate proportional to the frequency of said reference signal to provide a resultant count output, and divider means operably connected to said oscillator means and said counter means and having an output of said second signal; and wherein said oscillator means is common to each said phase-locked-loops.

Claim 11

A digital phase-locked-loop system for locking in phase a plurality of pairs of first and second signals each pair of substantially the same frequency comprising in combination: a plurality of phase-locked-loops each including, bistable means having an up-enable and a down-enable output responsive to certain phase angles of a first signal to set said bistable means to said up-enable output and responsive to the same phase angles of a second signal to reset said bistable means to said down-enable output; oscillator means for producing a reference signal having a frequency fr; counter means operably connected to said bistable means and said oscillator means for counting in one direction in response to said up-enable output and for counting in the opposite direction in response to said down-enable output at some counting rate proportional to the frequency of said reference signal to provide a resultant count output, and divider means operably connected to said oscillator means and said counter means and having an output of said second signal; and wherein said oscillator means is common to each said phase-locked-loops.