Self-checking decision logic circuit

Claim 2

A decision logic system comprising a check register having a plurality of data cells each having a true and a complement output, a mask register having a plurality of data cells each also having a true and a complement output, a plurality of first logic circuit means for individually combining said true outputs of said mask and check registers, respectively, in a NAND relationship for generating a plurality of true output signals, a plurality of second logic circuit means for individually combining said complement outputs of said mask and check registers, respectively, in a NOR relationship for generating a plurality of complement output signals, means for combining said true output signals in an AND relationship for generating an error-checking signal, and means for combining said complement output signals also in an AND relationship for generating a decision signal.

Claim 3

A decision logic system comprising a first register having a plurality of data cells each having a true and complement output representative of the contents of the cell, a second register having a plurality of data cells each also having a true and complement output representative of the contents of the cell, a plurality of NAND gate means each having a pair of inputs and an output, a plurality of NOR gate means each also having a pair of inputs and an output, the true outputs of corresponding cells of said first and second registers being applied respectively to the pair of inputs of each of said NAND gate means and the complement outputs of said corresponding cells of said first and second registers being applied respectively to the pair of inputs of each of said NOR gate means, first AND gate means having a plurality of inputs connected respectively to the outputs of said plurality of NAND gate means, and second AND gate means having a plurality of inputs connected respectively to the outputs of said plurality of NOR gate means.

Claim 4

A decision logic system comprising a first register having a plurality of data cells each having a true and complement output representative of the contents of the cell, a second register having a plurality of data cells each also having a true and complement output representative of the contents of the cell, a plurality of NAND gate means each having a pair of inputs and an output, a plurality of NOR gate means each also having a pair of inputs and an output, the true outputs of corresponding cells of said first and second registers being applied respectively to the pair of inputs of each of said NAND gate means and the complement outputs of said corresponding cells of said first and second registers being applied respectively to the pair of inputs of each of said NOR gate means, first AND gate means having a plurality of inputs connected respectively to the outputs of said plurality of NAND gate means, and second AND gate means having a plurality of inputs connected respectively to the outputs of said plurality of NOR gate means.

Claim 5

A decision logic system comprising a first and a second data register each having a plurality of data storage cells, means for comparing the contents of corresponding cells of said first and second data register comprising a toggle check register having a plurality of data storage cells, a first and a second plurality of gating means for successively gating the contents of said plurality of data storage cells of said first and said second data register to the corresponding cells of said check register for toggling and retoggling said last-mentioned cells, each of the storage cells of said check register having a true and a complement output indicative of the contents of a cell, a mask register having a plurality of data storage cells each also having a true and a complement output indicative of the contents of a cell, a plurality of first logic circuit means for individually combining said true outputs of said mask and check registers, respectively, in a NAND relationship for generating a plurality of true output signals, a plurality of second logic circuit means for individually combining said complement outputs of said mask and check registers, respectively, in a NOR relationship for generating a plurality of complement output signals, and gating means for combining each plurality of said true output signals and said complement output signals in an AND relationship to generate, respectively, an error-checking signal and a decision signal.

Claim 6

A decision logic system comprising a first and a second data register each having a plurality of data storage cells, means for comparing the contents of corresponding cells of said first and second data register comprising a toggle check register having a plurality of data storage cells, a first and a second plurality of gating means for successively gating the contents of said plurality of data storage cells of said first and said second data register to the corresponding cells of said check register for toggling and retoggling said last-mentioned cells, each of the storage cells of said check register having a true and a complement output indicative of the contents of a cell, a mask register having a plurality of data storage cells each also having a true and a complement output indicative of the contents of a cell, a plurality of first logic circuit means for individually combining said true outputs of said mask and check registers, respectively, in a NAND relationship for generating a plurality of true output signals, a plurality of second logic circuit means for individually combining said complement outputs of said mask and check registers, respectively, in a NOR relationship for generating a plurality of complement output signals, and gating means for combining each plurality of said true output signals and said complement output signals in an AND relationship to generate, respectively, an error-checking signal and a decision signal.

Claim 7

A decision logic system according to claim 3 also comprising controlled means having a first and a second operative state determined responsive to said decision signal, said controlled means providing a state signal indicative of said operative state, and error-checking circuit means for generating an error signal responsive to said error-checking signal and a particular state signal for generating an error signal.

Claim 8

A decision logic system according to claim 4 in which said controlled means comprises a control kit storage cell of a program data register, the operative state of which determines the instruction sequence of a data processor.

Claim 9

A decision logic system comprising a check register having a plurality of data storage cells containing a plurality of binary check bits, each of said cells having a true and a complement output, means for selecting a decision pattern of said check bits comprising a mask register having a plurality of data storage cells containing a plurality of binary mask bits, each of said last-mentioned cells also having a true and a complement output, and a plurality of NOR logic circuit means each having a first input connected to a complement output of a corresponding cell of said check register and a second input connected to a complement output of a corresponding cell of said mask register and each having a single output, and an AND logic circuit means having a plurality of inputs connected respectively to said outputs of said NOR logic circuit means for generating a decision logic signal.

Claim 10

A decision logic system comprising a check register having a plurality of data storage cells containing a plurality of binary check bits, each of said cells having a true and a complement output, means for selecting a decision pattern of said check bits comprising a mask register having a plurality of data storage cells containing a plurality of binary mask bits, each of said last-mentioned cells also having a true and a complement output, and a plurality of NOR logic circuit means each having a first input connected to a complement output of a corresponding cell of said check register and a second input connected to a complement output of a corresponding cell of said mask register and each having a single output, and an AND logic circuit means having a plurality of inputs connected respectively to said outputs of said NOR logic circuit means for generating a decision logic signal.

Claim 11

A decision logic system according to claim 6 in which said AND logic circuit means comprises a plurality of transistor NAND gates each having an input connected to an output of one of said NOR circuit means, the outputs of said NAND gates being collector-tied.

Claim 12

A decision logic system according to claim 6 also comprising a plurality of NAND logic circuit means each having a first input conneCted to a true output of a corresponding cell of said mask register and a second input connected to a true output of a corresponding cell of said check register and each having a single output and means for connecting the outputs of said NAND logic circuit means so that a single output signal is generated of a particular binary value if a signal of said particular binary value appears on any of said last-mentioned outputs of said plurality of NAND logic circuit means.

Claim 13

A decision logic system according to claim 8 also comprising apparatus controlled responsive to said decision logic signal for assuming a first and a second operative state and for generating a state signal indicative of said first and second state and circuit means operated responsive to said single output signal and said state signal for generating an error-checking signal.

Claim 14

In a data processing system, in combination, a first data register having a predetermined plurality of binary bits stored therein, a second data register having a predetermined second plurality of binary bits stored therein, a toggle check register having a plurality of storage cells each being initially in a clear state and each having a true and complement output indicative of the contents of the cell, means of toggling particular ones of said storage cells of said check register responsive to said first plurality of binary bits during one operative phase, means for retoggling said particular ones of said storage cells of said check register responsive to said second plurality of binary bits during another operative phase to leave particular check bits in said storage cells of said check register, means for selecting particular ones of said check bits as a condition for a logic decision comprising a mask register having a plurality of storage cells having a predetermined pattern of mask bits stored therein, each of said last-mentioned storage cells having a true and a complement output indicative of the contents of the cell, and a plurality of logic gating means for combining respectively corresponding complement outputs of the storage cells of said mask register and said check register for generating a plurality of NOR output signals; and a logic gating means for combining said NOR output signals in an AND relationship during a succeeding operative phase for generating a decision output signal.

Claim 15

In a data processing system, in combination, a first data register having a predetermined plurality of binary bits stored therein, a second data register having a predetermined second plurality of binary bits stored therein, a toggle check register having a plurality of storage cells each being initially in a clear state and each having a true and complement output indicative of the contents of the cell, means of toggling particular ones of said storage cells of said check register responsive to said first plurality of binary bits during one operative phase, means for retoggling said particular ones of said storage cells of said check register responsive to said second plurality of binary bits during another operative phase to leave particular check bits in said storage cells of said check register, means for selecting particular ones of said check bits as a condition for a logic decision comprising a mask register having a plurality of storage cells having a predetermined pattern of mask bits stored therein, each of said last-mentioned storage cells having a true and a complement output indicative of the contents of the cell, and a plurality of logic gating means for combining respectively corresponding complement outputs of the storage cells of said mask register and said check register for generating a plurality of NOR output signals; and a logic gating means for combining said NOR output signals in an AND relationship during a succeeding operative phase for generating a decision output signal.

Claim 16

In a data processing system, the combination as claimed in claim 10 also comprising a plurality of logic gating means for combining respectively corresponding true outputs of the storage cells of said mask register and said check register for generating a plurality of NAND output signals and means for combining said NAND output signals in an AND relationship during said succeeding operative phase for generating a check output signal.

Claim 17

In a data processing signal, the combination as claimed in claim 11 also comprising data processing controlled means operated responsive to said decision output signal to assume a first or a second operative state, said controlled means including means for generating a state signal indicative of one or the other of said operative states.

Claim 18

In a data processing system, the combination as claimed in claim 12 also comprising error-checking circuit means operated responsive to said check signal and said state signal for generating an error-checking signal.

Claim 19

In a data processing system, the combination as claimed in claim 13 in which said data processing controlled means comprises a program data register in which said first and second operative state determines the program instruction sequence of said system.