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US3778736A
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Channel selection system
Assignee: Panasonic Holdings Corp
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Filing: 1971-09-13
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Granted: 1973-12-11
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Expires: 1991-09-13
Abstract
Abstract A pair of memory circuits, each comprising four binary memory units, are connected to a matrix network for applying binary coded digital outputs of the memory circuits to a set of logic gates, for instance NAND-gates, which, in response to said output signals of the memory circuits, connect a selected voltagefeeding network to variable-capacitance diodes of selected tuning circuits.
Inventors
- 👤 Y Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:09
CPC Classifications
H; H03; H03J; H03J5/00; H03J5/02; H03J5/0218; H03J5/0227
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
A channel selection system for controlling tuners Which includes voltage responsive variable capacitance diodes as tuning elements, comprising a plurality of memory circuits, each of which includes four binary memory units, each memory circuit being capable of storing one digit of a decimal numeral in binary form, a matrix network having a plurality of input lines and a plurality of output lines, a plurality of logic gates corresponding to respective channels and being connected to respective matrix network output lines, said matrix network input lines being connected to respective binary memory units, and voltage imparting means connected between said logic gates and the variable capacitance diodes of said tuner for selectively applying respective voltage levels to said diodes in response to actuation of a selected logic gate.
Claim 2
Dependent Claim
127 words
A channel selection system for controlling tuners Which includes voltage responsive variable capacitance diodes as tuning elements, comprising a plurality of memory circuits, each of which includes four binary memory units, each memory circuit being capable of storing one digit of a decimal numeral in binary form, a matrix network having a plurality of input lines and a plurality of output lines, a plurality of logic gates corresponding to respective channels and being connected to respective matrix network output lines, said matrix network input lines being connected to respective binary memory units, and voltage imparting means connected between said logic gates and the variable capacitance diodes of said tuner for selectively applying respective voltage levels to said diodes in response to actuation of a selected logic gate.
Claim 3
Dependent Claim
51 words
A channel selection system as defined in claim 1, further including a decimal numeral indicator and conversion means connected between said binary memory units and said indicator for converting the binary signals stored in said memory units to signals to be applied to said indicator for indicating a decimal channel number.
Claim 4
Dependent Claim
38 words
A channel selection system as defined in claim 1, wherein said matrix network comprises a plurality of decimal-digital switches having inputs forming said input lines and outputs forming said output lines which are connected to respective logic gates.
Claim 5
Dependent Claim
50 words
A channel selection system as defined in claim 1 wherein said voltage imparting means includes a voltage source and a plurality of voltage dividing resistor pairs connected between respective logic gates and said voltage source each of said voltage dividing resistor pairs providing a voltage corresponding to an individual channel.
Claim 6
Dependent Claim
46 words
A channel selection system as defined in claim 1, further including a plurality of additional logic gates connected to respective matrix network output lines and switching means responsive to the outputs from said additional logic gates for controlling said tuner to shift the channel frequency bands.
Claim 7
Dependent Claim
53 words
A channel selection system as defined in claim 5, wherein at least one tuner includes an inductor having at least one tap connected to a semiconductor switching device and control means for controlling said switching device to short circuit said tap in response to outputs of selected ones of said additional logic gates.
Claim 8
Dependent Claim
97 words
A channel selection system as defined in claim 6, including a first NOR gate connected to the outputs of a first group of said additional logic gates for higher channels of the VHF band, a second NOR gate connected to the outputs of a second group of said additional logic gates for lower channels of the VHF band, a NAND gate connected to the outputs of said first and second NOR gates, and an electronic switch connected to said NAND gate for selectively connecting a voltage supply to one or the other of a pair of tuners.
Claim 9
Dependent Claim
51 words
A channel selection system as defined in claim 7, further including a decimal numeral indicator and conversion means connected between said binary memory units and said indicator for converting the binary signals stored in said memory units to signals to be applied to said indicator for indicating a decimal channel number.
Claim 10
Dependent Claim
38 words
A channel selection system as defined in claim 8, wherein said matrix network comprises a plurality of decimal-digital switches having inputs forming said input lines and outputs forming said output lines which are connected to respective logic gates.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |