Zero degree phase comparator

Claim 2

Apparatus for indicating the phase difference between first and second fluctuating signals comprising error magnitude detector means for generating a magnitude signal representative of the magnitude of the phase difference between said first and second signals, error sense detector means for generating a signal indicative of the sense of the phase difference between said first and second signals, pulse generating means responsive to both said detector means for generating error pulses having a polarity representing sense of the phase difference between said first and second signals and each also indicating magnitude of such phase difference, means for integrating said error pulses to provide an output error signal having a magnitude proportional to said phase difference and a polarity indicative of the sense of said phase difference, each of said first and second signals comprising three components of mutually different phases, said error magnitude detector means including means for generating a plurality of magnitude error signals, each respectively indicative of the magnitude of the phase difference between corresponding components of said first and second input signals, said pulse generating means comprising means for generating a pulse upon each occurrence of one of said error magnitude signals from said phase error magnitude detecting means, and said integrating means including means for integrating all of the pulses provided from said pulse generating means.

Claim 3

The apparatus of claim 1 wherein each component of each of said first and second signals comprises positive going and negative going part cycles, wherein said phase error magnitude detecting means includes means for generating a lead or lag pulse, one for each part cycle of each component of said first and second input signals, wherein said error sense detector means includes means responsive to each of said lead and lag pulses for gating said error magnitude signals so as to produce error magnitude signal pulses, separated according to error sense, on each part cycle of each component of said first and second signals, wherein said pulse generating means comprises means for generating a pulse having one polarity or the other in accordance with the sense of the phase difference between said first and second signals, said last mentioned pulse being generated once for each part cycle of each component of said first and second signals and having a width proportional to the magnitude of the phase difference between said first and second signals.

Claim 4

The apparatus of claim 2 including means for indicating when the width of said lead or lag pulse is less than a preselected amount to thereby indicate when the magnitude of the phase error is less than a predetermined magnitude.

Claim 5

Apparatus for indicating the phase difference between first and second alternating signals, each having positive going and negative going part cycles, said apparatus comprising first means for comparing positive going part cycles of each said first and second signals for generating a first lead-lag pulse representing both magnitude and sense of the phase difference between said positive going part cycles, second means for comparing negative going part cycles of said first and second input signals to generate a second lead-lag pulse indicating both magnitude and sense of the phase difference between said negative going part cycles, and means for combining said first and second lead-lag pulses to provide an output phase error signal representing both said lead-lag pulses, whereby said output phase error signal is based upon two comparisons for each full cycle of said first and second signals.

Claim 6

Apparatus for indicating the phase difference between first and second alternating signals, each having positive going and negative going part cycles, said apparatus comprising first means for comparing positive going part cycles of each said first and second signals for generating a first lead-lag pulse representing both magnitude and sense of the phase difference between said positive going part cycles, second means for comparing negative going part cycles of said first and second input signals to generate a second lead-lag pulse indicating both magnitude and sense of the phase difference between said negative going part cycles, and means for combining said first and second lead-lag pulses to provide an output phase error signal representing both said lead-lag pulses, whereby said output phase error signal is based upon two comparisons for each full cycle of said first and second signals.

Claim 7

The apparatus of claim 4 wherein said first and second signals each comprises at least a pair of phase displaced components, each said component having positive and negative going part cycles, wherein saiD means for comparing said positive going part cycles includes means for comparing a positive going part cycle of the first component of said first signal with a positive going part cycle of the first component of said second signal, and means for comparing the positive going part cycle of the second component of said first signal with the positive going part cycle of the second component of said second signal, thereby to generate first and second positive part cycle error signals respectively representing magnitude and sense of the phase difference between positive going part cycles of first and second components of said first and second signals, wherein said means for comparing negative going part cycles of said first and second signals comprises means for comparing the negative going part cycle of said first component of the first signal with the negative going part cycle of the first component of the second signal and means for comparing the negative going part cycle of the second component of the first signal with the negative going part cycle of the second component of the second signal, thereby to generate first and second negative part cycle error signals respectively representing the magnitude and sense of the phase difference between the negative going part cycles of the first and second components of said first and second signals, and wherein said means for combining said lead-lag pulses comprises means for combining all of said positive going and negative going part cycle error signals thereby to provide an output signal bearing information based upon a plurality of different part cycle signal component comparisons.

Claim 8

A zero degree phase synchronizer for synchronizing a variable multiphase rectangular wave signal with either a first or a second multiphase rectangular wave reference signal comprising reference switching means for selectively providing components of either said first or second reference signals, a plurality of phase error magnitude detectors, each individual to a different component of the signals to be compared, each said detector comprising an exclusive Or gate having a first input from one component of said variable signal and a second input from a corresponding component of the chosen reference signal, and providing error magnitude pulses, a plurality of lead-lag detecting circuits, each individual to a pair of corresponding components of said variable and chosen reference signals, each lead-lag detector comprising means for generating a selector signal that represents that one of the components of the variable and chosen reference frequencies being compared by the individual detector that has a predetermined phase sense relative to the other of such components, and means for comparing said selector signal with both positive and negative going part cycles of said components being compared to obtain a pair of phase error sense signals for each full cycle of said components being compared, means for sequentially gating the phase error sense signals generated by said plurality of lead-lag circuits, means for sequentially combining the magnitude pulses from said plurality of phase error magnitude detectors, means for identifying said error magnitude pulses in accordance with the sense of said phase error sense signals, and means for averaging said error magnitude pulses so as to provide an output error signal containing information derived from two comparisons for each cycle of each component of said reference signal.

Claim 9

A zero degree phase synchronizer for synchronizing a variable multiphase rectangular wave signal with either a first or a second multiphase rectangular wave reference signal comprising reference switching means for selectively providing components of either said first or second reference signals, a plurality of phase error magnitude detectors, each individual to a different component of the signals to be compared, each said detector comprising an exclusive Or gate having a first input from one component of said variable signal and a second input from a corresponding component of the chosen reference signal, and providing error magnitude pulses, a plurality of lead-lag detecting circuits, each individual to a pair of corresponding components of said variable and chosen reference signals, each lead-lag detector comprising means for generating a selector signal that represents that one of the components of the variable and chosen reference frequencies being compared by the individual detector that has a predetermined phase sense relative to the other of such components, and means for comparing said selector signal with both positive and negative going part cycles of said components being compared to obtain a pair of phase error sense signals for each full cycle of said components being compared, means for sequentially gating the phase error sense signals generated by said plurality of lead-lag circuits, means for sequentially combining the magnitude pulses from said plurality of phase error magnitude detectors, means for identifying said error magnitude pulses in accordance with the sense of said phase error sense signals, and means for averaging said error magnitude pulses so as to provide an output error signal containing information derived from two comparisons for each cycle of each component of said reference signal.

Claim 10

The apparatus of claim 6 wherein said means for sequentially combining said error magnitude pulses comprises pulse generator means for generating a pulse of a first polarity for each said error magnitude pulse that is identified by said lead-lag detecting circuits to represent a phase error of a first sense and generating a pulse of opposite polarity for each of said error magnitude pulses that is identified by said lead-lag detecting circuits to represent a phase erroR of opposite sense, and means for integrating pulses produced by said pulse generating means.

Claim 11

The apparatus of claim 6 including means responsive to the sense and magnitude of said detected phase error for changing said variable frequency signal in a sense to cause the phase difference to approach zero degrees.

Claim 12

The apparatus of claim 7 including means for indicating the sense and magnitude of the output of said integrating means.

Claim 13

The apparatus of claim 8 including means for comparing the magnitude of the phase error indicated by said error magnitude pulses with a predetermined error magnitude to provide an output indicating that the phase difference between said variable frequency signal and the chosen one of said reference signals is less than said predetermined magnitude.

Claim 18

The method of claim 12 including the step of generating error signals representing a phase difference between said first and second fluctuating signals of a second sense opposite to said first sense, said last mentioned step comprising the steps of generating a third error signal when said first (A1) and selector (Q1) signals occur together in the absence of said second (A3) signal, and generating a fourth error signal when said second (A3) signal occurs in the absence of both said first (A1) and said selector (Q1) signals.

Claim 19

The method of claim 12 wherein said steps of generating said first and second error signals includes the step of generating each of said first and second error signals for a time substantially equal to the magnitude of the phase difference between said first (A1) and second (A3) signals.

Claim 20

The method of claim 13 including the step of separately presenting said first and second error signals and said third and fourth error signals so as to provide separated representations of respectively opposite sense phase differences between said first (A1) and second (A3) signals.

Claim 21

A phase comparator for first and second substantially rectangular wave signals comprising means for generating a selector signal that coincides with the lagging one of said first and second signals, and means for combining said selector signal with both said first and second signals to indicate noncoincidence of the leading one of said signals with both said selector signal and the lagging one of said first and second signals.

Claim 22

A phase comparator for first and second substantially rectangular wave signals comprising means for generating a selector signal that coincides with the lagging one of said first and second signals, and means for combining said selector signal with both said first and second signals to indicate noncoincidence of the leading one of said signals with both said selector signal and the lagging one of said first and second signals.

Claim 23

A phase comparator for comparing first and second Substantially rectangular wave signals comprising a bi-state device connected to be set to a first state by coincidence of said first and second signals and to be reset to a second state upon the fall of the lagging one of said first and second signals, a first coincidence gate (G21) having as inputs thereto a signal representing the reset state of said device, a signal representing the absence of said first signal and a signal representing the presence of said second input signal, a second coincidence gate (G20) having as inputs thereto a signal representing the set state of said device, a signal representing presence of said first input signal and a signal representing absence of said second input signal, a third coincidence gate (G23) having a first input representing the reset state of said device, a second input representing presence of said first input signal and a third input representing absence of said second input signal, a fourth coincidence gate (G22) having an input representing the set state of said device, an input representing the absence of said first input signal and an input representing the presence of said second input signal, means for combining the outputs of said first and second coincidence gates to provide an output representation of a first sense phase difference between said first and second square wave signals, and means for combining the outputs of said third and fourth coincidence gates to provide a second input representation of a phase difference of opposite sense between said first and second square wave signals.

Claim 24

A phase comparator for comparing first and second Substantially rectangular wave signals comprising a bi-state device connected to be set to a first state by coincidence of said first and second signals and to be reset to a second state upon the fall of the lagging one of said first and second signals, a first coincidence gate (G21) having as inputs thereto a signal representing the reset state of said device, a signal representing the absence of said first signal and a signal representing the presence of said second input signal, a second coincidence gate (G20) having as inputs thereto a signal representing the set state of said device, a signal representing presence of said first input signal and a signal representing absence of said second input signal, a third coincidence gate (G23) having a first input representing the reset state of said device, a second input representing presence of said first input signal and a third input representing absence of said second input signal, a fourth coincidence gate (G22) having an input representing the set state of said device, an input representing the absence of said first input signal and an input representing the presence of said second input signal, means for combining the outputs of said first and second coincidence gates to provide an output representation of a first sense phase difference between said first and second square wave signals, and means for combining the outputs of said third and fourth coincidence gates to provide a second input representation of a phase difference of opposite sense between said first and second square wave signals.

Claim 27

The method of claim 18 wherein each of said input signals comprises at least two mutually phased displaced components and wherein said step of detecting magnitude of the phase difference includes the steps of detecting magnitude of the phase error between a first component of said first input signal and a first component of said second input signal, and also detecting the magnitude of the phase error between a second component of said first input signal and the second component of said second input signal.

Claim 28

The method of claim 19 wherein said step of combining the detected error magnitude and phase error comprises means for producing a plurality of pulses, each representing magnitude of the phase error but separated according to the detected sense of the phase error, and further including means for integrating said pulses to provide said output phase error signal.

Claim 29

A zero degree phase comparator for comparing the sense and magnitude of the phase error between first and second rectangular wave signals comprising lead detector means for generating a series of lead pulses each representing noncoincidence of said first and second signals whenever a leading relation exists between said first and second signals, said lead pulses each having a duration representative of the duration of such noncoincidence between said first and second signals, lag detector means for generating a series of lag pulses each representing noncoincidence of said first and second signals whenever a lagging relation exists between said first and second signals, each said lag pulse having a duration representing the duration of noncoincidence between said first and second signals, pulse generator means for generating a plurality of pulses, each representing the duration of one of said lead or lag pulses and each having one polarity or another in accordance with whether said lead or lag pulses are produced by said lead and lag detector means, each of said lead detector means and lag detector means comprising means for generating a selector signal that coincides with that one of said first and second signals that has a predetermined phase sense relative to the other, and means for combining said selector signal with said first and second signals to obtain said lead or lag pulses.

Claim 30

A zero degree phase comparator for comparing the sense and magnitude of the phase error between first and second rectangular wave signals comprising lead detector means for generating a series of lead pulses each representing noncoincidence of said first and second signals whenever a leading relation exists between said first and second signals, said lead pulses each having a duration representative of the duration of such noncoincidence between said first and second signals, lag detector means for generating a series of lag pulses each representing noncoincidence of said first and second signals whenever a lagging relation exists between said first and second signals, each said lag pulse having a duration representing the duration of noncoincidence between said first and second signals, pulse generator means for generating a plurality of pulses, each representing the duration of one of said lead or lag pulses and each having one polarity or another in accordance with whether said lead or lag pulses are produced by said lead and lag detector means, each of said lead detector means and lag detector means comprising means for generating a selector signal that coincides with that one of said first and second signals that has a predetermined phase sense relative to the other, and means for combining said selector signal with said first and second signals to obtain said lead or lag pulses.