US3778643A
Expired / Lapsed
US
⏱️ 0.0 years remaining
A solid state variable delay line using reversed biased pn junctions
Assignee: Motors Liquidation Co
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Filing: 1972-05-18
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Granted: 1973-12-11
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Expires: 1992-05-18
Abstract
Abstract An electronically variable delay line including a wafer of silicon on one side of which a thin insulating layer is deposited. A highly conducting ground plane contacts the silicon wafer on its remaining side while a highly conducting microstrip line contacts the insulating layer. The microstrip line contacts the silicon wafer through small holes etched in the insulating layer at predetermined intervals. At these holes, P-N junctions are formed. The P-N junctions are reverse biased so as to vary the effective thickness of the insulating layer to vary the delay time by creating a depletion layer within the silicon wafer which acts as an effective insulator.
Inventors
- 👤 J Jaffe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:45
CPC Classifications
H; H03; H03H; H03H7/00; H03H7/30; H03H7/34; H03H7/345
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
176 words
An electronically variable delay line comprising a semiconductor body; a conducting ground plane contacting the semiconductor on one side thereof; an insulator contacting the semiconductor body on another side thereof; a transmission line conductor carried by the insulator, said insulator having openings therein which are spaced along and under the transmission line conductor so that the transmission line conductor contacts the semiconductor body through said insulator, the portions of the semiconductor body contacted by the transmission line conductor being of one conductivity type with the remaining portion of the semiconductor body being of the opposite conductivity type, said portions combining to form a plurality of diode junctions; and variable bias voltage means coupled to the conducting ground plane and the transmission line conductor and poled to reverse bias the diode junctions to form a depletion layer within the semiconductor body which combines with the insulator to form an effective insulator having a width which varies as the function of the magnitude of the bias voltage to thereby vary the delay time of the variable delay line.
Claim 2
Dependent Claim
176 words
An electronically variable delay line comprising a semiconductor body; a conducting ground plane contacting the semiconductor on one side thereof; an insulator contacting the semiconductor body on another side thereof; a transmission line conductor carried by the insulator, said insulator having openings therein which are spaced along and under the transmission line conductor so that the transmission line conductor contacts the semiconductor body through said insulator, the portions of the semiconductor body contacted by the transmission line conductor being of one conductivity type with the remaining portion of the semiconductor body being of the opposite conductivity type, said portions combining to form a plurality of diode junctions; and variable bias voltage means coupled to the conducting ground plane and the transmission line conductor and poled to reverse bias the diode junctions to form a depletion layer within the semiconductor body which combines with the insulator to form an effective insulator having a width which varies as the function of the magnitude of the bias voltage to thereby vary the delay time of the variable delay line.
Claim 3
Dependent Claim
158 words
An electronically variable delay line system comprising: a variable delay line including a semiconductor body having a first portion composed of one conductivity type and a second portion composed of the opposite conductivity type, the first and second portions combining to form a diode junction, a conducting ground plane contacting the first portion of the semiconductor body, a transmission line conductor contacting the second portion of the semiconductor body and variable bias voltage means coupled to the conducting ground plane and the transmission line conductor and poled to reverse bias the diode junction to form a depletion layer having a variable thickness; a signal generator for generating a signal having a frequency less than a critical frequency below which the variable delay line becomes dispersionless; and means coupling the signal to the variable delay line whereby the signal is delayed by the variable delay line for a time duration determined by the reverse bias on the diode junction.
Claim 4
Dependent Claim
158 words
An electronically variable delay line system comprising: a variable delay line including a semiconductor body having a first portion composed of one conductivity type and a second portion composed of the opposite conductivity type, the first and second portions combining to form a diode junction, a conducting ground plane contacting the first portion of the semiconductor body, a transmission line conductor contacting the second portion of the semiconductor body and variable bias voltage means coupled to the conducting ground plane and the transmission line conductor and poled to reverse bias the diode junction to form a depletion layer having a variable thickness; a signal generator for generating a signal having a frequency less than a critical frequency below which the variable delay line becomes dispersionless; and means coupling the signal to the variable delay line whereby the signal is delayed by the variable delay line for a time duration determined by the reverse bias on the diode junction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |