Patent US3778540A successfully refreshed from Google Patents.
US3778540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic electronic here is generator
Assignee: Individual
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Filing: 1972-04-20
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Granted: 1973-12-11
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Expires: 1992-04-20
Abstract
Abstract A ''''here is'''' generator, for an automatic answering data terminal, which generates a WRU code and applies it to the terminal''s answer-back mechanism. The generator has a square wave oscillator and a pair of timing circuits which initially free the oscillator for oscillation then clamp it in a mark output and finally clamp it in a steady state space output.
Inventors
- 👤 R Fretwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:57
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/02; H04L12/06
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
198 words
A ''''here is'''' generator apparatus for generating a WRU code at its output in response to a pulse at its input, comprising: a. a square pulse oscillator for generating alternative output levels corresponding to mark and space pulses and having a mark clamping input and a space clamping input, the output of said oscillator being the output of said apparatus; b. a first timing circuit means having its input connected to the apparatus input for generating an output level shift for a selected first time interval; c. a second timing circuit means having it input connected to the apparatus input for generating an output level shift for a selected second time interval, the output of said second timing means connected to said mark clamping input for clamping the oscillator at a mark output except during said second time period; and d. an ''''exclusive or'''' gate means having its output connected to said space clamping input and a pair of inputs eAch connected to the output of one of said timing circuit means for clamping said oscillator at a space output level when only one of the timing circuit means outputs is in its said output level shifted condition.
Claim 2
Dependent Claim
198 words
A ''''here is'''' generator apparatus for generating a WRU code at its output in response to a pulse at its input, comprising: a. a square pulse oscillator for generating alternative output levels corresponding to mark and space pulses and having a mark clamping input and a space clamping input, the output of said oscillator being the output of said apparatus; b. a first timing circuit means having its input connected to the apparatus input for generating an output level shift for a selected first time interval; c. a second timing circuit means having it input connected to the apparatus input for generating an output level shift for a selected second time interval, the output of said second timing means connected to said mark clamping input for clamping the oscillator at a mark output except during said second time period; and d. an ''''exclusive or'''' gate means having its output connected to said space clamping input and a pair of inputs eAch connected to the output of one of said timing circuit means for clamping said oscillator at a space output level when only one of the timing circuit means outputs is in its said output level shifted condition.
Claim 3
Dependent Claim
34 words
An apparatus according to claim 1 wherein said first time interval is more than four and less than five pulse lengths in duration and said second time interval is eight pulse lengths in duration.
Claim 4
Dependent Claim
37 words
An apparatus according to claim 2 wherein said apparatus input is connected to the output of a modem carrier detector and said apparatus output is connected to an input of a modem WRU code detector logic circuit.
Claim 5
Dependent Claim
123 words
An apparatus according to claim 3 wherein one of said timing circuit means comprises: a. a high gain differential comparator having one of its inputs adjustably biased to a selected voltage level; b. a serially connected timing capacitance, charging resistance and dc source having the other comparator input connected to the node intermediate said resistance and said capacitance; c. a capacitance discharge circuit comprising a series transistor switch and discharge resistance connected parallel to said capacitance and having a control input terminal for discharging said capacitance in response to a pulse at said control input; and d. a differentiator circuit connected between said apparatus input and said control input for differentiating a square pulse and applying the differentiated pulse to said transistor switch.
Claim 6
Dependent Claim
53 words
An apparatus according to claim 3 wherein said ''''exclusive or'''' gate means comprises: a. a high gain differential comparator having one of its inputs biased to a selected voltage level; and b. a pair of diodes each connected between the other comparator input and the output of one of said timing circuit means.
Claim 7
Dependent Claim
139 words
An apparatus according to claim 3 wherein said oscillator comprises: a. a first high gain differential comparator having an inverting input, a non-inverting input and an output; b. a first voltage divider feedback network connected to said output, to a common ground and to said non-inverting input for applying a proportion of the signal at said output to said non-inverting input; c. a second feedback network including a series connected pair of resistances connected between said output and said inverting input, and a capacitance connected between the common node of said resistance pair and a dc source; d. a first diode having its cathode connected to said common node and its anode connected to said mark clamping input; and e. a second diode having its cathode connected to said non-inverting input and its anode connected said space clamping input.
Claim 8
Dependent Claim
62 words
An apparatus according to claim 6 wherein said ''''exclusive or'''' gate means comprises: a. a second high gain differential comparator having its non-inverting input biased to a selected voltage level; and b. a pair of diodes having their cathodes connected to the inverting input of said comparator and each of their cathodes connected to a different one of said timing circuit means.
Claim 9
Dependent Claim
134 words
An apparatus according to claim 7 wherein said first timing circuit means comprises: a. a third high gain differential comparator having its non-inverting input biased to a selected voltage level; b. a serially connected first timing capacitance, first charging resistance and first dc source, having the comparator inverting input connected to the node intermediate said first resistance and said first capacitance; c. a capacitance discharge circuit comprising a series first transistor switch and first discharge resistance connected parallel to said first capacitance and having a first control input terminal for discharging said capacitance in response to a pulse at said first control input; and d. a first differentiator circuit connected between said apparatus input and said first control input for differentiating a square pulse and applying the differentiated pulse to said first tranSistor switch.
Claim 10
Dependent Claim
138 words
An apparatus according to claim 8 wherein said second timing circuit means comprises: a. a fourth high gain differential comparator having its non-inverting input biased to a selected voltage level; b. a serially connected second timing capacitance, second charging resistance and second dc source, having said fourth comparator''s inverting input connected to the node intermediate said second resistance and said second capacitance; c. a capacitance discharge circuit comprising a series second transistor switch and second discharge resistance connected parallel to said second timing capacitance and having a second control input terminal for discharging said second timing capacitance in response to a pulse at said second control input; and d. a second differentiator circuit connected between said apparatus input and said second control input for differentiating a square pulse and applying the differentiated pulse to said second transistor switch.
Claim 11
Dependent Claim
112 words
An apparatus according to claim 1 further including means for activating the answer back mechanism of a Teletype terminal, the terminal having a WRU code detector for activating the answer back mechanism in response to the occurrence of the WRU code at its input, the apparatus comprising: a. said means a carrier detector means for shifting its output level in response to the receipt of a carrier from a remote terminal; and b. a WRU code generating circuit means connected to the output of said carrier detector means for generating a WRU code in response to said level shift and having its output connected to an input to said WRU code detector.
References Cited (Backward Citations)
US3531772A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-10 | 1977-06-11 | 1977-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-10 | 1981-06-11 | 1981-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-10 | 1985-06-11 | 1985-12-11 | $7700.00 | Window Closed / Lapsed |