Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
158 words
A digital time rate measuring system for a timing device comprising: means for receiving timing signals from the timing device wherein one timing signal is defined as a start timing signal and a subsequent timing signal is defined as a stop timing signal; reference clock pulse means; first gating means for defining a first interval of reference clock pulses equispaced on either side of a median reference pulse and timed to include said stop timing signal; means responsive to the time sequence of occurrence of said median reference pulse and said stop timing signal during said first interval; second gating means for defining a second interval within said first interval between the times of occurrence of said reference pulse and said stop timing signal; deviation clock pulse means for providing a deviation time rate, and counting means connected to said deviation clock pulse means for counting the absolute number of deviation clock pulses occurring during said second interval.
Claim 2
Dependent Claim
158 words
A digital time rate measuring system for a timing device comprising: means for receiving timing signals from the timing device wherein one timing signal is defined as a start timing signal and a subsequent timing signal is defined as a stop timing signal; reference clock pulse means; first gating means for defining a first interval of reference clock pulses equispaced on either side of a median reference pulse and timed to include said stop timing signal; means responsive to the time sequence of occurrence of said median reference pulse and said stop timing signal during said first interval; second gating means for defining a second interval within said first interval between the times of occurrence of said reference pulse and said stop timing signal; deviation clock pulse means for providing a deviation time rate, and counting means connected to said deviation clock pulse means for counting the absolute number of deviation clock pulses occurring during said second interval.
Claim 3
Dependent Claim
26 words
A system as in claim 1 wherein said reference clock pulse means is of a greater accuracy and higher frequency than said deviation clock pulse means.
Claim 4
Dependent Claim
25 words
A system as in claim 1 wherein said reference clock pulse means and said deviation clock pulse means are supplied from the same clock source.
Claim 5
Dependent Claim
63 words
A system as in claim 1 wherein said first gating means further includes counting means for counting the number of reference clock pulses, decode means for detecting the median reference pulse and the pulses at the lower end and upper end of said first interval and circuit means turned on by the lower end pulse and turned off by the upper end pulse.
Claim 6
Dependent Claim
67 words
A system as in claim 1 wherein said means responsive to the time sequence includes circuit means having two stable states wherein said circuit means is placed in a first state when said reference pulse precedes said stop timing signal indicating a lag condition and said circuit means is placed in a second state when said stop timing signal precedes said reference pulse indicating a lead condition.
Claim 7
Dependent Claim
33 words
A system as in claim 1 wherein said second gating means includes circuit means which can be turned on and subsequently turned off by both said reference pulse and said stop timing signal.
Claim 8
Dependent Claim
37 words
A system as in claim 1 and further including decode means coupled to said counting means for detecting a predetermined number of deviation clock pulses and in response thereto terminating the operation of said second gating means.
Claim 9
Dependent Claim
39 words
A system as in claim 4 wherein said means for receiving further includes pick-up means coupled to the timing device, amplifying means receiving the output from said pick-up means, and pulsing means connected to the output of said amplifier.
Claim 10
Dependent Claim
15 words
A system as in claim 1 wherein said means for receiving includes frequency dividing means.
Claim 11
Dependent Claim
77 words
A system as in claim 9 wherein said frequency dividing means further includes, a plurality of decimal counter for counting the timing signals; a plurality of decimal decoders connected to corresponding ones of said decimal counters and each including switch means for selecting the number to be decoded; output means for producing an output pulse when all said decoders have decoded the selected numbers; and reset means responsive to said output pulse for resetting said decimal counters.