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US3775696A
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Synchronous digital system having a multispeed logic clock oscillator
Assignee: Texas Instruments Inc
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Filing: 1971-11-18
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Granted: 1973-11-27
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Expires: 1991-11-18
Abstract
Abstract A multispeed synchronous digital system, such as a digital data processing system, includes a multispeed logic clock oscillator for producing a synchronizing clock signal. A plurality of multiinput ECL NAND gates, one for each system speed, have a common clock output. The clock output is connected in feedback relationship through cumulative time delays to the NAND gate inputs. A system operating speed is determined according to a logic control signal input to the NAND gates, with the logic control signal functioning as a speed select signal. Speed select signals are adaptable to be controlled under manual or program execution control. Adjustable delay lines enable selective adjustment of clock pulse width, and hence clock frequency for each of the plurality of system speeds.
Inventors
- 👤 E Garth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:12
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; Y; Y10; Y10S; Y10S331/00; Y10S331/03
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
136 words
A multispeed logic clock oscillator operable to produce a logic clock signal of a selected controlled frequency in response to a speed select signal, comprising: a. a plurality of bilevel devices, including at least first and second bilevel devices, having a common clock output and each having a clock input and an enabling input cOupled to receive said speed select signal; b. a first signal delay means coupling said common clock output to the clock input of said first bilevel device; c. a second signal delay means coupling the clock input of said first bilevel device to the clock input of said second bilevel device; and d. for the remaining bilevel devices in succession, a signal delay means coupling the clock input of a prior bilevel device to the clock input of the successive bilevel device.
Claim 2
Dependent Claim
136 words
A multispeed logic clock oscillator operable to produce a logic clock signal of a selected controlled frequency in response to a speed select signal, comprising: a. a plurality of bilevel devices, including at least first and second bilevel devices, having a common clock output and each having a clock input and an enabling input cOupled to receive said speed select signal; b. a first signal delay means coupling said common clock output to the clock input of said first bilevel device; c. a second signal delay means coupling the clock input of said first bilevel device to the clock input of said second bilevel device; and d. for the remaining bilevel devices in succession, a signal delay means coupling the clock input of a prior bilevel device to the clock input of the successive bilevel device.
Claim 3
Dependent Claim
19 words
a first signal delay means coupling said common clock output to the clock input of said first bilevel device;
Claim 4
Dependent Claim
19 words
a first signal delay means coupling said common clock output to the clock input of said first bilevel device;
Claim 5
Dependent Claim
21 words
The logic clock oscillator of claim 1 wherein at least one of said signal delay means is an adjustable delay line.
Claim 6
Dependent Claim
43 words
The logic clock oscillator of claim 2 wherein said adjustable delay line is comprised of a plurality of segments of transmission line connecting pairs of plated terminals in a printed circuit board, adaptable to be selectively interconnected to introduce a cumulative time delay.
Claim 7
Dependent Claim
24 words
a second signal delay means coupling the clock input of said first bilevel device to the clock input of said second bilevel device; and
Claim 8
Dependent Claim
24 words
a second signal delay means coupling the clock input of said first bilevel device to the clock input of said second bilevel device; and
Claim 9
Dependent Claim
29 words
for the remaining bilevel devices in succession, a signal delay means coupling the clock input of a prior bilevel device to the clock input of the successive bilevel device.
Claim 10
Dependent Claim
29 words
for the remaining bilevel devices in succession, a signal delay means coupling the clock input of a prior bilevel device to the clock input of the successive bilevel device.
Claim 11
Dependent Claim
18 words
The logic clock oscillator of claim 3 wherein said segments of transmission line are binary weighted in length.
Claim 12
Dependent Claim
27 words
The logic clock oscillator of claim 3 wherein said adjustable delay line further comprises at least one logic circuit for enhancing the integrity of the clock pulse.
Claim 13
Dependent Claim
17 words
The logic clock oscillator of claim 1 wherein said bilevel devices are multiple input ECL NAND gates.
Claim 14
Independent Claim
76 words
A method of adjusting the operating speed of a synchronous digital system comprising: a. coupling a common output terminal of a plurality of bilevel devices through successive time delay means to the input terminals of said bilevel devices; b. selectively enabling one of said bilevel devices which corresponds to a desired system operating speed; and c. operating the selected bilevel device to continuously produce an output signal which is the inverse of the input signal thereto.
Claim 15
Independent Claim
76 words
A method of adjusting the operating speed of a synchronous digital system comprising: a. coupling a common output terminal of a plurality of bilevel devices through successive time delay means to the input terminals of said bilevel devices; b. selectively enabling one of said bilevel devices which corresponds to a desired system operating speed; and c. operating the selected bilevel device to continuously produce an output signal which is the inverse of the input signal thereto.
Claim 16
Dependent Claim
31 words
The method of claim 7 further comprising the step of adjusting the time delay introduced by at least one of said time delay means to adjust said desired system operating speed.
Claim 17
Dependent Claim
51 words
A synchronous digital system comprising: a. a plurality of logic cards located throughout said system, said logic cards including thereon a plurality of logic circuits coupled to be operatively controlled by a system clock signal; and b. a multispeed logic clock oscillator operable to produce said system clock signal and comprising:
Claim 18
Dependent Claim
51 words
A synchronous digital system comprising: a. a plurality of logic cards located throughout said system, said logic cards including thereon a plurality of logic circuits coupled to be operatively controlled by a system clock signal; and b. a multispeed logic clock oscillator operable to produce said system clock signal and comprising:
Claim 19
Dependent Claim
48 words
The system of claim 9 wherein at least one of said signal delay means is an adjustable delay line comprised of a plurality of transmission line segments connecting pairs of plated terminals in a printed circuit board, adaptable to be selectively interconnected to introduce a cumulative time delay.
Claim 20
Dependent Claim
15 words
The system of claim 10 wherein said transmission line segments are binary weighted in length.
References Cited (Backward Citations)
US3248657A
Cited
US3295138A
Cited
US3497712A
Cited
US3418498A
Cited
US3411107A
Cited
US3562558A
Cited
US3543185A
Cited
US3624519A
Cited
US3619669A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-26 | 1977-05-28 | 1977-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-26 | 1981-05-28 | 1981-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-26 | 1985-05-28 | 1985-11-27 | $7700.00 | Window Closed / Lapsed |