Control circuit for generating output signal of specified duration at specified delay after receiving input signal

Claim 2

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said trigger circuit comprising: a. first and second DC power leads, including a positive and a negative lead; b. a first and a second transistor, including a PNP and an NPN transistor; c. said first transistor having its base connected to said ''''set'''' input and its emitter to said first lead; d. a first resistor connected between the collector of said first transistor and said second lead; e. said second transistor having its base connected to the collector of said first transistor, and its collector connected to said trigger output; f. a second resistor connected between the collector of said second transistor and said first lead; g. a diode connected between the emitter of said second transistor and said second lead; and h. a third transistor having its base connected to said ''''reset'''' input, and having its collector and emitter connected between the base of said first transistor and said first lead.

Claim 3

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said timer circuit comprising: a. positive and negative DC power leads; b. a third lead including means for connecting said third lead to said positive lead; c. first, second and third SCRs; d. first and second UJTs; e. first and second PNP transistors; f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output; g. a first resistor connected between the base-one termianl of said first UJT and said negative lead; h. a first variable resistor connected between the base-two termianl of said first UJT and said delay output; i. a first capacitor connected between the emitter of said first UJT and said negative lead; j. a second variable resistor connected between the emitter of said first transistor and said third lead; k. the collector of said first transistor being connected to the emitter of said first UJT; l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor; m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output; n. a second resistor connected between the base-one terminal of said second UJT and said negative lead; o. a third variable resistor connected between the base-two terminal of said second UJT and said duration output; p. a second capacitor connected between the emitter of said second UJT and said negative lead; q. a fourth variable resistor connected between the emitter of said second transistor and said third lead; r. the collector of said second transistor being connected to the emitter of said second UJT; s. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.

Claim 4

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said timer circuit comprising: a. positive and negative DC power leads; b. a third lead including means for connecting said third lead to said positive lead; c. first, second and third SCRs; d. first and second UJTs; e. first and second PNP transistors; f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output; g. a first resistor connected between the base-one termianl of said first UJT and said negative lead; h. a first variable resistor connected between the base-two termianl of said first UJT and said delay output; i. a first capacitor connected between the emitter of said first UJT and said negative lead; j. a second variable resistor connected between the emitter of said first transistor and said third lead; k. the collector of said first transistor being connected to the emitter of said first UJT; l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor; m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output; n. a second resistor connected between the base-one terminal of said second UJT and said negative lead; o. a third variable resistor connected between the base-two terminal of said second UJT and said duration output; p. a second capacitor connected between the emitter of said second UJT and said negative lead; q. a fourth variable resistor connected between the emitter of said second transistor and said third lead; r. the collector of said second transistor being connected to the emitter of said second UJT; s. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.

Claim 5

A control circuit according to claim 2 further comprising: a third capacitor connected between the cathodes of said first and second SCRs; and a fourth capacitor connected between the cathodes of said second and thirds SCRs.

Claim 6

A control circuit according to claim 3 further comprising: a fifth capacitor connected between said timer input and the gate of said first SCR; and a sixth capacitor connected between the cathode of said third SCR and the ''''reset'''' input of said trigger circuit.

Claim 7

A control circuit according to claim 2 further comprising: a first diode connected in said voltage divider between said third lead and said intermediate point; and said third lead connecting means including a second diode connected between said positive lead and said third lead.

Claim 8

A control circuit according to claim 2 wherein said trigger circuit comprises: a''. first and second DC power leads, including a positive and a negative lead; b''. a first and a second transistor, including a PNP and an NPN transistor; c''. said first transistor having its base connected to said ''''set'''' input and its emitter to said first lead; d''. a first resistor connected between the collector of said first transistor and said second lead; e''. said second transistor having its base connected to the collector of said first transistor and its collector connected to said trigger output; f''. a second resistor connected between the collector of said second transistor and said first lead; g''. a diode connected between the emitter of said second transistor and said second lead; and h''. a third transistor having its base connected to said ''''reset'''' input, and having its collector and emitter connected between the base of said first transistor and said first lead.

Claim 9

A control circuit according to claim 2 further comprising: a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.

Claim 10

A timer circuit according to claim 7 further comprising: a second transistor having its collector connected to the collector of said power transistor, its emitter connected to the base of said power transistor, and its base connected to said output of said timer circuit.

Claim 11

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.

Claim 12

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a bi-stable trigger circuit having a ''''set'''' input for receiving said input signal, a ''''reset'''' input for receiving a reset signal, and an output; a delay-duration interval timer circuit having an input connected to the output of said trigger circuit, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.

Claim 13

A timer circuit according to claim 9 further comprising: a second transistor having its collector connected to the collector of said power transistor, its emitter connected to the base of said power transistor, and its base connected to said output of said timer circuit.

Claim 14

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a dElay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said timer circuit comprising: a. positive and negative DC power leads; b. a third lead including means for connecting said third lead to said positive lead; c. first, second and third SCRs; d. first and second UJTs; e. first and second PNP transistors; f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output; g. a first resistor connected between the base-one terminal of said first UJT and said negative lead; h. a first variable resistor connected between the base-two terminal of said first UJT and said delay output; i. a first capacitor connected between the emitter of said first UJT and said negative lead; j. a second variable resistor connected between the emitter of said first transistor and said third lead; k. the collector of said first transistor being connected to the emitter of said first UJT; l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor; m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output; n. a second resistor connected between the base-one terminal of said second UJT and said negative lead; o. a third variable resistor connected between the base-two terminal of said second UJT and said duration output; p. a second capacitor connected between the emitter of said second UJT and said negative lead; q. a fourth variable resistor connected between the emitter of said second transistor and said third lead; r. the collector of said second transistor being connected to the emitter of said second UJT; s. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.

Claim 15

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a dElay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; said timer circuit comprising: a. positive and negative DC power leads; b. a third lead including means for connecting said third lead to said positive lead; c. first, second and third SCRs; d. first and second UJTs; e. first and second PNP transistors; f. said first SCR having its gate connected to said timer input, its anode connected to said positive lead and its cathode connected to said delay output; g. a first resistor connected between the base-one terminal of said first UJT and said negative lead; h. a first variable resistor connected between the base-two terminal of said first UJT and said delay output; i. a first capacitor connected between the emitter of said first UJT and said negative lead; j. a second variable resistor connected between the emitter of said first transistor and said third lead; k. the collector of said first transistor being connected to the emitter of said first UJT; l. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said first transistor; m. said second SCR having its gate connected to the base-one terminal of said first UJT, its anode connected to said positive lead and its cathode connected to said duration output; n. a second resistor connected between the base-one terminal of said second UJT and said negative lead; o. a third variable resistor connected between the base-two terminal of said second UJT and said duration output; p. a second capacitor connected between the emitter of said second UJT and said negative lead; q. a fourth variable resistor connected between the emitter of said second transistor and said third lead; r. the collector of said second transistor being connected to the emitter of said second UJT; s. a voltage divider connected between said third lead and said negative lead, and having an intermediate point connected to the base of said second transistor; and t. said third SCR having its gate connected to the base-one terminal of said second UJT and its anode connected to said positive lead.

Claim 16

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a delay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.

Claim 17

A control circuit for generating an output signal of a specified duration at a specified delay after receiving an input signal, said circuit comprising: a delay-duration interval timer circuit having an input connected for receiving said input signal, a delay output for presenting an output signal only during the delay interval, and a duration output for producing an output signal only during the duration interval; and a power output circuit having a''''. a pair of output leads; b''''. a pair of DC power leads; c''''. a capacitor connected between one of said output leads and one of said power leads; d''''. a resistor connected between said one of said output leads and the other of said power leads; e''''. a power transistor having its collector and emitter terminals connected between the other of said output leads and said one of said power leads; and f''''. said power transistor having its base connected to an output of said timer circuit.