Conversion of nrz data to self-clocking data

Claim 3

The combination of claim 1 further comprising means receiving said reproduced signal to generate an error signal when said reproduced signal falls below a predetermined amplitude level.

Claim 4

The combination of claim 1 wherein said encoder means comprises means for storing two successive NRZ bits, whereby the first of said bits is a delayed NRZ bit, means receiving said clock signal for delaying said clock signal one-half bit, means for providing a flux transition when a delayed NRZ bit and a delayed clock signal are true or when the two successive NRZ bits are not true and the clock signal is true.

Claim 5

The combination of claim 1 wherein said decoder means comprises means for storing said self-clocking information for one bit time, and means for detecting the slope of said stored waveform during the first one-half bit and the second one-half bit of said bit time and for providing a signal of one sense when said slopes are different.

Claim 6

The combination of claim 4 wherein said decoder means further comprises means for detecting peaks occurring at the end of said one bit storage time, to provide a signal of one sense in response thereto, and means receiving said peak responsive signals for providing a clock signal.

Claim 7

An encoder for providing self-clocking modified NRZ signal in which a transition occurs in the middle of a bit cell to represent a 1 and a transition occurs between bit cells representing two successive O''s in response to an input NRZ signal and clock signal comprising means for storing two successive NRZ bits, whereby the first of said bits is a delayed NRZ bit, means receiving said clock signal for delaying said clock signal one-half bit, means for providing a flux transition when a delayed NRZ bit and a delayed clock signal are true or when the two successive NRZ bits are not true and the clock signal is true.

Claim 8

An encoder for providing self-clocking modified NRZ signal in which a transition occurs in the middle of a bit cell to represent a 1 and a transition occurs between bit cells representing two successive O''s in response to an input NRZ signal and clock signal comprising means for storing two successive NRZ bits, whereby the first of said bits is a delayed NRZ bit, means receiving said clock signal for delaying said clock signal one-half bit, means for providing a flux transition when a delayed NRZ bit and a delayed clock signal are true or when the two successive NRZ bits are not true and the clock signal is true.

Claim 9

An encoder for providing self-clocking modified NRZ signal in which a transition occurs in the middle of a bit cell to represent a 1 and a transition occurs between bit cells representing two successive O''s in response to an input NRZ signal and clock signal comprising means for storing two successive NRZ bits, whereby the first of said bits is a delayed NRZ bit, means for providing a true signal when the two successive stored NRZ bits are O''s, means receiving said clock signal for providing a flux transition when said true signal and clock signal are simultaneous, means receiving said clock signal for delaying said clock signal one-half bit, and means receiving said one-half bit delayed clock signal and the last stored NRZ bit for providing a flux transition when said last stored NRZ bit is a 1 and is simultaneous with said one-half bit delayed clock signal.

Claim 10

An encoder for providing self-clocking modified NRZ signal in which a transition occurs in the middle of a bit cell to represent a 1 and a transition occurs between bit cells representing two successive O''s in response to an input NRZ signal and clock signal comprising means for storing two successive NRZ bits, whereby the first of said bits is a delayed NRZ bit, means for providing a true signal when the two successive stored NRZ bits are O''s, means receiving said clock signal for providing a flux transition when said true signal and clock signal are simultaneous, means receiving said clock signal for delaying said clock signal one-half bit, and means receiving said one-half bit delayed clock signal and the last stored NRZ bit for providing a flux transition when said last stored NRZ bit is a 1 and is simultaneous with said one-half bit delayed clock signal.

Claim 11

A decoder for providing an NRZ signal and clock sigNal in response to a waveform having transitions which occur in the middle of a bit cell to represent a 1 and transitions which occur between bit cells representing two successive O''s comprising means for providing a pulse in response to each peak in said waveform, means phase locked to said waveform peaks for providing clock signals of first and second phases, means for selecting the correct clock signal phase as the output clock signal, and means receiving said pulses and the other clock signal phase for providing an NRZ output signal.

Claim 12

A decoder for providing an NRZ signal and clock sigNal in response to a waveform having transitions which occur in the middle of a bit cell to represent a 1 and transitions which occur between bit cells representing two successive O''s comprising means for providing a pulse in response to each peak in said waveform, means phase locked to said waveform peaks for providing clock signals of first and second phases, means for selecting the correct clock signal phase as the output clock signal, and means receiving said pulses and the other clock signal phase for providing an NRZ output signal.

Claim 13

The combination of claim 8 further comprising means for generating an error signal when the waveform amplitude falls below a predetermined level.

Claim 14

A decoder for providing an NRZ signal and clock signal in response to a waveform having transitions which occur in the middle of a bit cell to represent a 1 and transitions which occur between bit cells representing two successive O''s comprising means for providing a pulse in response to each peak in said waveform, means phase locked to said pulses for providing first clock signals and second clock signals delayed one-half bit from said first clock signals, means receiving said pulses and one of said clock signals for providing an output NRZ signal, means for providing said other clock signals as the output clock signal, and means for reversing said clock signals in response to a 101 code sequence when the output clock signal phase is incorrect.

Claim 15

A decoder for providing an NRZ signal and clock signal in response to a waveform having transitions which occur in the middle of a bit cell to represent a 1 and transitions which occur between bit cells representing two successive O''s comprising means for providing a pulse in response to each peak in said waveform, means phase locked to said pulses for providing first clock signals and second clock signals delayed one-half bit from said first clock signals, means receiving said pulses and one of said clock signals for providing an output NRZ signal, means for providing said other clock signals as the output clock signal, and means for reversing said clock signals in response to a 101 code sequence when the output clock signal phase is incorrect.

Claim 16

The combination of claim 10 wherein said phase locked means includes a flywheel type oscillator and further comprising means for removing said pulses from said phase locked means when the waveform amplitude falls below a predetermined level.