US3774166A — Short-range data processing transfers

Claim 1

Independent Claim 66 words

The method of controlling a data processor comprising the steps of: 1. addressing a memory for instructions, including transfer instructions; 2. extracting the addressed instructions from said memory; 3. forming an address of said memory by displacing a fractional portion of a pre-existing address with a portion of an extracted transfer instruction; and 4. addressing said memory with the address thus formed for the next instruction.

Claim 2

Independent Claim 66 words

The method of controlling a data processor comprising the steps of: 1. addressing a memory for instructions, including transfer instructions; 2. extracting the addressed instructions from said memory; 3. forming an address of said memory by displacing a fractional portion of a pre-existing address with a portion of an extracted transfer instruction; and 4. addressing said memory with the address thus formed for the next instruction.

Claim 3

Dependent Claim 7 words

extracting the addressed instructions from said memory;

Claim 4

Dependent Claim 7 words

extracting the addressed instructions from said memory;

Claim 5

Dependent Claim 12 words

storing the electrical signals representing an addressed instruction in an instruction register;

Claim 6

Dependent Claim 12 words

storing the electrical signals representing an addressed instruction in an instruction register;

Claim 7

Dependent Claim 23 words

The method as defined in claim 1 wherein displacing portions of extracted transfer instructions are accumulated over at least two cycles of operation.

Claim 8

Dependent Claim 12 words

storing the electrical signals representing each addressed instruction in an instruction register;

Claim 9

Dependent Claim 12 words

storing the electrical signals representing each addressed instruction in an instruction register;

Claim 10

Dependent Claim 31 words

Enabling selected memory address gates, responsive to the contents of said program address register, to address a selected processor memory location containing a transfer instruction in the form of electrical signals;

Claim 11

Dependent Claim 31 words

Enabling selected memory address gates, responsive to the contents of said program address register, to address a selected processor memory location containing a transfer instruction in the form of electrical signals;

Claim 12

Dependent Claim 17 words

storing said transfer instruction signals in the instruction register of said processor, via said enabled address gates;

Claim 13

Dependent Claim 17 words

storing said transfer instruction signals in the instruction register of said processor, via said enabled address gates;

Claim 14

Dependent Claim 51 words

forming an address of said memory, when electrical signals representing a transfer instruction are present in said instruction register, by replacing a fractional portion of a set of electrical signals contained in the program address register of said processor with a portion of the electrical signals in said instruction register; and

Claim 15

Dependent Claim 51 words

forming an address of said memory, when electrical signals representing a transfer instruction are present in said instruction register, by replacing a fractional portion of a set of electrical signals contained in the program address register of said processor with a portion of the electrical signals in said instruction register; and

Claim 16

Independent Claim 18 words

The method of controlling the sequence of operations performed by an electronic data processor comprising the steps of:

Claim 17

Independent Claim 18 words

The method of controlling the sequence of operations performed by an electronic data processor comprising the steps of:

Claim 18

Dependent Claim 39 words

storing a portion of the electrical signals constituting a first transfer instruction extracted from said memory in a storage register by enabling selected gates when said electrical signals constituting said first transfer instructon are present in said instruction register;

Claim 19

Dependent Claim 39 words

storing a portion of the electrical signals constituting a first transfer instruction extracted from said memory in a storage register by enabling selected gates when said electrical signals constituting said first transfer instructon are present in said instruction register;

Claim 20

Dependent Claim 24 words

forming an address of said memory by displacing a fractional portion of a pre-existing address with a portion of an extracted transfer instruction; and

Claim 21

Dependent Claim 24 words

forming an address of said memory by displacing a fractional portion of a pre-existing address with a portion of an extracted transfer instruction; and

Claim 22

Dependent Claim 12 words

addressing said memory with the address thus formed for the next instruction.

Claim 23

Dependent Claim 12 words

addressing said memory with the address thus formed for the next instruction.

Claim 24

Dependent Claim 74 words

Apparatus comprising storage means, means for addressing said storage means to extract signals therefrom, means for storing a portion of a first set of signals extracted from said storage means, means for extracting a second set of signals from said storage means, and means for partially displacing the signals in the addressing means with said stored signals and selected ones of the second set of signals to form the address of a nonsequential instruction.

Claim 25

Dependent Claim 74 words

Apparatus comprising storage means, means for addressing said storage means to extract signals therefrom, means for storing a portion of a first set of signals extracted from said storage means, means for extracting a second set of signals from said storage means, and means for partially displacing the signals in the addressing means with said stored signals and selected ones of the second set of signals to form the address of a nonsequential instruction.

Claim 26

Dependent Claim 48 words

forming an address of said memory by replacing a fractional portion of a pre-existing address thereof, contained in a program address register, with the stored portion of saId first transfer instruction and with a portion of electrical signals representing a second transfer instruction extracted from said memory; and

Claim 27

Dependent Claim 48 words

forming an address of said memory by replacing a fractional portion of a pre-existing address thereof, contained in a program address register, with the stored portion of saId first transfer instruction and with a portion of electrical signals representing a second transfer instruction extracted from said memory; and

Claim 28

Dependent Claim 32 words

displacing a fractional portion of the contents of said program address register with a first portion of said transfer instruction by enabling gates responsive to a second portion of said transfer instruction;

Claim 29

Dependent Claim 32 words

displacing a fractional portion of the contents of said program address register with a first portion of said transfer instruction by enabling gates responsive to a second portion of said transfer instruction;

Claim 30

Dependent Claim 12 words

addressing said memory with the address thus formed for the next instruction.

Claim 31

Dependent Claim 12 words

addressing said memory with the address thus formed for the next instruction.

Claim 32

Dependent Claim 12 words

addressing said memory with the address thus formed for the next instruction.

Claim 33

Dependent Claim 12 words

addressing said memory with the address thus formed for the next instruction.

Claim 34

Dependent Claim 31 words

enabling selected memory address gates with the modified contents of said program address register to address a selected memory location containing a new instruction in the form of electrical signals; and

Claim 35

Dependent Claim 31 words

enabling selected memory address gates with the modified contents of said program address register to address a selected memory location containing a new instruction in the form of electrical signals; and

Claim 36

Dependent Claim 70 words

Apparatus comprising a memory with a plurality of storage locations for groups of signals representing program instructions, including transfer instructions, means for generating signals sequentially addressing the storage locations of said program instructions, means for extracting the addressed signals, including transfer signals, from said memory, and means for modifying a fractional portion of the address signals with a portion of said transfer signals to form the address of an instruction.

Claim 37

Dependent Claim 70 words

Apparatus comprising a memory with a plurality of storage locations for groups of signals representing program instructions, including transfer instructions, means for generating signals sequentially addressing the storage locations of said program instructions, means for extracting the addressed signals, including transfer signals, from said memory, and means for modifying a fractional portion of the address signals with a portion of said transfer signals to form the address of an instruction.

Claim 38

Dependent Claim 58 words

Apparatus comprising a program store, a register for addressing said program store, means for incrementing the addresses of said register, a register for storing the addressed contents of said program store, and means for partially replacing the contents of the address register with a portion of the contents of the storage register to form a nonsequential instruction address.

Claim 39

Dependent Claim 58 words

Apparatus comprising a program store, a register for addressing said program store, means for incrementing the addresses of said register, a register for storing the addressed contents of said program store, and means for partially replacing the contents of the address register with a portion of the contents of the storage register to form a nonsequential instruction address.

Claim 40

Dependent Claim 19 words

replacing said transfer instruction signals in said instruction register with said new instruction signals via said enabled address gates.

Claim 41

Dependent Claim 19 words

replacing said transfer instruction signals in said instruction register with said new instruction signals via said enabled address gates.

Claim 42

Dependent Claim 55 words

In an apparatus having an addressable store, the improvement comprising, control means for directing a transfer to a nonsequential location in said store, which means supplies a fractional portion of a store address, and combining means responsive to said control means for replacing an equivalent portion of a pre-existing store address with said fractional portion.

Claim 43

Dependent Claim 55 words

In an apparatus having an addressable store, the improvement comprising, control means for directing a transfer to a nonsequential location in said store, which means supplies a fractional portion of a store address, and combining means responsive to said control means for replacing an equivalent portion of a pre-existing store address with said fractional portion.

Claim 44

Dependent Claim 44 words

The improvement of claim 7 wherein said control means includes means for successively supplying at least two fractional portions of a store address, and said combining means includes means for replacing an equivalent portion of said pre-existing address with all of said fractional portions.

Claim 45

Dependent Claim 20 words

The improvement of calim 8 further comprising, means for accumulating said fractional portions over at least two cycles of operation.

Claim 46

Dependent Claim 20 words

The improvement of calim 8 further comprising, means for accumulating said fractional portions over at least two cycles of operation.

Claim 47

Dependent Claim 72 words

In a general purpose digital computer having an address register of given length for providing access to an addressable store, the improvement comprising, means for extracting a transfer instruction from said store, and means responsive to said transfer instruction for replacing a portion of said address register with a portion of said transfer instruction, which portion is of less length than the length of said address register, to obtain a nonsequential address.

Claim 48

Dependent Claim 72 words

In a general purpose digital computer having an address register of given length for providing access to an addressable store, the improvement comprising, means for extracting a transfer instruction from said store, and means responsive to said transfer instruction for replacing a portion of said address register with a portion of said transfer instruction, which portion is of less length than the length of said address register, to obtain a nonsequential address.

Claim 49

Independent Claim 18 words

The method of controlling the sequence of operations performed by an electronic data processor comprising the steps of:

Claim 50

Independent Claim 18 words

The method of controlling the sequence of operations performed by an electronic data processor comprising the steps of:

Claim 51

Independent Claim 18 words

The method of controlling the sequence of operations performed by an electronic data processor comprising the steps of:

Claim 52

Independent Claim 18 words

The method of controlling the sequence of operations performed by an electronic data processor comprising the steps of:

Claim 53

Dependent Claim 77 words

The method of claim 12 wherein the number of bit positions in said instruction register occupied by the operand of said transfer instruction is less than the number of bits in a full memory address and step (4) further comprises; modifying the contents of said program address register by gating each of the electrical signals occupying the set of instruction register bit positions containing said operand directly into a selected bit position of said program address register.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-11-19	1977-05-21	1977-11-20	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-11-19	1981-05-21	1981-11-20	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-11-19	1985-05-21	1985-11-20	$7700.00	Window Closed / Lapsed

Short-range data processing transfers

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