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Solid state switching and memory apparatus

Assignee: Fairchild Semiconductor Corp
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Filing: 1969-07-02
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Granted: 1973-11-13
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Expires: 1989-07-02
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Abstract

Abstract A memory cell having two transistors, each transistor having two emitters, a base, and a collector; the bases and the collectors of the transistors are cross-coupled; by the application of a first signal to one of the emitters of each of the two transistors simultaneously, and a second signal at the same time to the other emitter of only one of the two transistors, the transistor having the second signal at its emitter is placed in a conducting state so that data is stored in the cell having the actuated emitter.

Inventors

  • 👤 R Norman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 12:18
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; H03K3/29; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/135

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 95 words
A memory cell comprising a pair to transistors each having a first and second emitter, a base and a collector; means for directly cross-coupling the collectors and the bases of said transistors; means for applying a first signal simultaneously to said first emitters of each of said transistors; and means for applying a second signal selectively through the second emitter of one of said transistors during the time said first signal is present to place the corresponding transistor in a conducting state whereby data is stored in said cell corresponding to the actuated second emitter.
Claim 2
Dependent Claim 95 words
A memory cell comprising a pair to transistors each having a first and second emitter, a base and a collector; means for directly cross-coupling the collectors and the bases of said transistors; means for applying a first signal simultaneously to said first emitters of each of said transistors; and means for applying a second signal selectively through the second emitter of one of said transistors during the time said first signal is present to place the corresponding transistor in a conducting state whereby data is stored in said cell corresponding to the actuated second emitter.
Claim 3
Dependent Claim 96 words
A memory cell comprising a pair of transistors each having a first and a second emitter, a base and a collector; means for directly cross-coupling the collectors and the bases of said transistors; means for setting the memory cell to one stable state; readout means for indicating the state of said memory cell, and means for applying a readout signal simultaneously to said second emitter of each transistor so that the state of said memory cell is indicated selectively through one of said first emitters corresponding to the state of said cell to said readout means.
Claim 4
Dependent Claim 96 words
A memory cell comprising a pair of transistors each having a first and a second emitter, a base and a collector; means for directly cross-coupling the collectors and the bases of said transistors; means for setting the memory cell to one stable state; readout means for indicating the state of said memory cell, and means for applying a readout signal simultaneously to said second emitter of each transistor so that the state of said memory cell is indicated selectively through one of said first emitters corresponding to the state of said cell to said readout means.

References Cited (Backward Citations)

US3218613A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-11-12 1977-05-14 1977-11-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-11-12 1981-05-14 1981-11-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-11-12 1985-05-14 1985-11-13 $7700.00 Window Closed / Lapsed

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