Lock-out circuit

Claim 2

A lock-out circuit comprising a plurality of inputs and a plurality of outputs to which bistate devices are connected such that only one bistate device is operated irrespective of the number of inputs which may simultaneously be activated, said circuit having two series of outputs and means coupling said bistate devices to a distinct pair of outputs from said two series.

Claim 3

A lock-out circuit according to claim 1, in which each of said bistate devices has only two terminals and may be operated by a change in the current flowing between the two paired outputs.

Claim 4

A lock-out circuit according to claim 1, characterized in that it includes a first and a second lock-out arrangement, the operation of said second lock-out arrangement being enabled only after the correct operation of said first lock-out arrangement, and that each of said inputs is connected via a common resistance and decoupling diodes to a distinct pair of input terminals from a first and a second series of input terminals of said first and said second lock-out arrangement having said first and second series of outputs in such a manner that a group of inputs is coupled to each input terminal, each of said lock-out arrangements being adapted to activate only one of its outputs irrespective of the number of its input terminals which may simultaneously be activated, said first lock-out arrangement when operated preventing all the inputs which are not connected to the input terminal corresponding to the activated output from activating the input terminals of the two lock-out arrangements to which they are connected.

Claim 5

A lock-out circuit according to claim 3, characterized in that it includes a check circuit the input of which is connected to said first lock-out arrangement and which is adapted to check if all except one of the input terminals of said first lock-out arrangement have been prevented from being activated, said check circuit having an output which is coupled to said second lock-out arrangement and which controls the operation thereof.

Claim 6

A lock-out circuit according to claim 4, characterized in that the output of said check circuit is connected to a timing circuit forming part of a double test circuit, said timing circuit being triggered to its operative condition for a predetermined time interval during which it enables the operation of said double test circuit when said check circuit has operated successfully, and the thus operated double test circuit enabling via gating means the operation of said second lock-out arrangement, and that said lock-out circuit is associated to a similar second lock-out circuit which has said plurality of inputs and which includes first and second lock-out arrangements, a check circuit, and a double test circuit with a timing circuit which are similar to those included in said first lock-out circuit, said double test circuits being intercoupled in such a way that only one of them can be operated simultaneously.

Claim 7

A lock-out circuit according to claim 3, characterized in that in said first lock-out arrangement each input terminal is coupled to temporary lock-out means and to definitive lock-out means, the temporary and definitive lock-out means coupled to an input terminal being successively operated when this one input terminal is activated due to which temporary and definitive inhibiting potentials are applied to all the input terminals, said one input terminal excepted.

Claim 8

A lock-out circuit according to claim 3, characterized in that said first lock-out arrangement is constituted by a plurality of third lock-out arrangements which are each coupled to the input terminals of an associated group of the groups of input terminals in which said first series is subdivided and by a fourth lock-out arrangement which is coupled to all the input terminals of said groups, each of said third lock-out arrangements being adapted when an input terminal of the associated group is activated to inhibit all but said input terminal of the associated group of input terminals and said fourth lock-out arrangement being adapted to inhibit the input terminals of all but those of said associated group of input terminals. .

Claim 9

A lock-out circuit according to claim 6, characterized in that in each of said third lock-out arrangements each input terminal of the associated group is coupled via an individual first resistance to first temporary lock-out means and is associated to first definitive lock-out means, while in said fourth lock-out arrangement the input terminals of each of said groups are each coupled at least via an individual second resistance to second temporary lock-out means which are associated to said group which is itself associated to second definitive lock-out means, and that said first temporary and definitive lock-out means when successively operated due to the associated input terminal of a group of input terminals being activated are adapted to successively apply first temporary and definitive inhibiting potentials to all the input terminals except said associated input terminal of said group, while said second temporary and definitive lock-out means when successively operated due to an input terminal of the associated group being activated are adapted to successively apply second temporary and definitive inhibiting potentials to all the input terminals except to those of said associated group.

Claim 10

A lock-out means according to claim 8, characterized in that said first definitive lock-out means associated to an input terminal of a group of input terminals are only operated after the first and second temporary lock-out means associated to said input terminal and to said group have been operated.

Claim 11

A lock-out circuit according to claim 8, characterized in that in each of said third lock-out arrangements each input terminal of the associated group is coupled via a said first resistance to the first input of an associated first AND-gate the second input of which is coupled to said first temporary inhibiting potential and the output of which is coupled to all the input terminals except said associated input terminal of said group via first diodes and that in said fourth lock-out arrangement all the input terminals of each of said groups are each coupled at least via a said second resistance to the first input of an associated second AND-gate the second input of which is coupled to said second temporary inhibiting potential and the output of which is coupled to all the input terminals except to those of said associated group via second diodes.

Claim 12

A lock-out circuit according to claim 10, characterized in that each of said input terminals is coupled to the first input of a said second AND-gate via the series connection of a said first and a said second resistance.

Claim 13

A lock-out circuit according to claim 10, characterized in that Said second diodes are coupled to those ends of said second resistance which are not connected to said first resistances.

Claim 14

A lock-out circuit according to claim 9, characterized in that in each of said third lock-out arrangements a third and a fourth AND-gate are associated to each of said first AND-gates, while in said fourth lock-out arrangement a fifth and a sixth AND-gate are associated to each of said second AND-gates and hence to each of said groups, that the output of each of said second AND-gates is coupled to the first input of ther associated fifth and sixth AND-gates the second inputs of which are coupled to a second definitive inhibiting potential and to an output activating potential respectively, the output of said fifth gate being connected via third diodes to all the input terminals of the other groups to which said fifth gate is not associated and the output of said sixth gate being connected to the first input of the third AND-gate associated to one input terminal of the group of input terminals to which said second AND-gate is associated, that the second input of said third AND-gate is coupled to the output of the first AND-gate which is connected to said one input terminal, the output of said third AND-gate being coupled to the first input of a fourth AND-gate and that the second input of said fourth AND-gate is coupled to a first definitive inhibiting potential, while its output is coupled via said first diodes to the other input terminals, of said group, to which the first AND-gate associated to said third AND-gate is not connected.

Claim 15

A lock-out circuit according to claim 13, characterized in that the output of each of said third AND-gates constitutes an output of said first lock-out arrangement.

Claim 16

A lock-out circuit according to claim 10, characterized in that each of said input terminals is connected via the series connection of said first and second resistances and of a third resistance to one pole of a first DC source the other pole of which is connected to an input of the lock-out circuit when the latter input is activated, and that the first and second tapping points between said first and second and between said second and third resistances respectively are connected to the first inputs of said first and second AND-gates respectively.

Claim 17

A lock-out circuit according to claim 13, characterized in that the output of each of said second AND-gates is coupled to the first inputs of the associated fifth and sixth AND-gates via an amplifier circuit.

Claim 18

A lock-out circuit according to claim 10, characterized in that each of said AND-gates is constituted by a transistor.

Claim 19

A lock-out circuit according to claim 16, characterized in that said amplifier circuit is constituted by a transistor.

Claim 20

A lock-out circuit according to claim 8, characterized in that said first and second temporary inhibiting potentials are different from each other.

Claim 21

A lock-out circuit according to claim 8, characterized in that said second temporary inhibiting potential and said first and second definitive inhibiting potentials are equal.

Claim 22

A lock-out circuit according to claim 3, characterized in that each of the input terminals of said second lock-out arrangement is coupled to the first input of an associated gate of a plurality of seventh AND-gates, each seventh AND-gate having a second input which is coupled to an enabling potential and having an output which is coupled via fourth diodes to all the input terminals of said second lock-out arrangement, except to the one to which the first input of said seventh AND-gate is coupled.

Claim 23

A lock-out circuit according to claim 20, characterized in that each of said input terminals is coupled to the first input of a said seventh AND-gate via an amplifier circuit.

Claim 24

A lock-out circuit according to claim 5, characterized in that the second inputs of said seventh AND-gates are coupled in common to said gating means which when activated provide Said enabling potential.

Claim 25

A lock-out circuit according to claim 21, characterized in that the output of each of said seventh AND-gates is coupled to the first input of an associated one of a plurality of eighth AND-gates, each eighth AND-gate having a second input which is coupled to an associated one of the outputs of said second lock-out arrangement and an output which is coupled to an activating potential.

Claim 26

A lock-out circuit according to claim 24, characterized in that the output of each of said eighth AND-gates is coupled to the first input of an associated one of a plurality of ninth AND-gates, each ninth AND-gate having a second input which is coupled to a third inhibiting potential and an output which is coupled to the output of an associated seventh AND-gate.

Claim 27

A lock-out circuit according to claim 5, characterized in that the outputs of said eighth AND-gates are coupled to said gating means in such a way that the latter are maintained activated when at least one of said outputs of said eighth AND-gates is activated, independently from the condition of said double test circuit.

Claim 28

A lock-out circuit according to claim 4, characterized in that the outputs of said eighth AND-gates are coupled to said check circuit in such a way that the latter is inhibited when at least one of said outputs of said eighth AND-gates is activated.

Claim 29

A lock-out circuit according to claim 21, characterized in that each of the input terminals of said second lock-out arrangement is connected via the series connection of a fourth and a fifth resistance to one pole of a DC source the other pole of which is connected to an input of the look-out circuit when the latter input is activated, and that the tapping point between each of said interconnected fourth and fifth resistances is coupled to the first input of a distinct one of said seventh AND-gates.

Claim 30

A lock-out circuit according to claim 21, characterized in that any of said AND-gates is constituted by a transistor.

Claim 31

A lock-out circuit according to claim 21, characterized in that said amplifier circuit is constituted by a transistor.

Claim 32

A lock-out circuit according to claim 21, characterized in that each of the m input terminals of said second lock-out arrangement is coupled to all but an associated one of the outputs of said seventh AND-gates via fourth diodes due to each input terminal being coupled via fourth diodes to p out of q wires, Cpq being at least equal to m, and due to those p wires being coupled also via fourth diodes to all the outputs of said seventh AND-gates, except to that of the associated seventh AND-gate.

Claim 33

A lock-out circuit with a plurality of inputs and with a plurality of outputs and such that only one output is activated irrespective of the number of inputs which may simultaneously be activated, characterized in that each input is coupled to temporary lock-out means and to definitive lock-out means, the temporary and definitive lock-out means coupled to an input being successively operated when this one input is activated due to which temporary and definitive inhibiting potentials are applied to all the inputs, said one input terminal excepted.

Claim 34

A lock-out circuit with a plurality of inputs and with a plurality of outputs and such that only one output is activated irrespective of the number of inputs which may simultaneously be activated, characterized in that each input is coupled to temporary lock-out means and to definitive lock-out means, the temporary and definitive lock-out means coupled to an input being successively operated when this one input is activated due to which temporary and definitive inhibiting potentials are applied to all the inputs, said one input terminal excepted.

Claim 35

A lock-out circuit according to claim 32, characterized in that each of said inputs is coupled to the associated temporary lock-out means via a resistance.

Claim 36

A lock-out circuit with a plurality of inputs and with a plurality of outputs such that only one output is activated irrespective of the number of inputs which may simultaneously be activated, characterized in that it is constituted by a plurality of first lock-out arrangements which are each coupled to the inputs of an associated group of the groups of inputs wherein said inputs are subdivided and by a second lock-out arrangement which is coupled to all the inputs of said groups, each of said first lock-out arrangements being adapted when an input of the associated group is activated to Inhibit all but said input of the associated group of inputs and said second lock-out arrangement being adapted to inhibit the inputs of all but those of said associated group of inputs.

Claim 37

A lock-out circuit with a plurality of inputs and with a plurality of outputs such that only one output is activated irrespective of the number of inputs which may simultaneously be activated, characterized in that it is constituted by a plurality of first lock-out arrangements which are each coupled to the inputs of an associated group of the groups of inputs wherein said inputs are subdivided and by a second lock-out arrangement which is coupled to all the inputs of said groups, each of said first lock-out arrangements being adapted when an input of the associated group is activated to Inhibit all but said input of the associated group of inputs and said second lock-out arrangement being adapted to inhibit the inputs of all but those of said associated group of inputs.

Claim 38

A lock-out circuit with m inputs and a plurality of outputs and such that only one output is activated irrespective of the number of inputs which may be simultaneously activated, characterized in that each of said m inputs is coupled on the one hand to the input of an associated one of a plurality of bistate devices and on the other hand via diodes to p out of q wires, the number of combinations Cpq being at least equal to m and said p wires being coupled via further diodes to all the outputs of the bistate devices except to that of the associated bistate deivce, in such a manner that when a said input is activated the associated bistate device is operated due to which an inhibiting potential is applied to all the inputs, except said activated one.

Claim 39

A lock-out circuit with m inputs and a plurality of outputs and such that only one output is activated irrespective of the number of inputs which may be simultaneously activated, characterized in that each of said m inputs is coupled on the one hand to the input of an associated one of a plurality of bistate devices and on the other hand via diodes to p out of q wires, the number of combinations Cpq being at least equal to m and said p wires being coupled via further diodes to all the outputs of the bistate devices except to that of the associated bistate deivce, in such a manner that when a said input is activated the associated bistate device is operated due to which an inhibiting potential is applied to all the inputs, except said activated one.