US3772597A — Code transmission system

Claim 1

Independent Claim 383 words

A binary code transmission system comprising a keyboard means including a plurality of key members, each of said key members being selectively depressable to one of a plurality of positions to select each of an assigned plurality of characters to be transmitted, a read-only memory means including means to store an assigned multi-bit code word therein for each of said plurality of characters to be transmitted, addressing means responsive to each depression of said key members to effect readout of the stored multi-bit code word assigned to that key depression, transmitter means including a transmitter modulator means, control means responsive to said keyboard depressions to activate said transmitter means, said transmitter modulator means receiving said stored code word readout from said read-only memory and developing in response thereto a corresponding modulating waveform, said transmitter means being responsive to said modulating waveform to transmit a carrier wave signal modulated in accordance therewith, said control means including means responsive to the completion of the readout of the last bit of predetermined coded message addressed from said read-only memory to deactivate said transmitter means; said control means comprising a source of clock pulses, logic means receiving said clock pulses and being responsive to said keyboard depressions to apply said clock pulses to said read-only memory to effect a serial readout from said read-only memory of said multi-bit code word assigned to that key depression, said read out being effected at a rate defined by said clock pulses, and said logic means comprising means to inhibit application of said clock pulses to said read-only memory upon application thereto of a number of clock pulses corresponding in number to the number of bits comprising each said multi-bit code word; said multi-bit code words comprising a plurality of 2N-1 bits each, said logic means comprising an N bit continuous binary counter having a rest state exhibiting a binary zero count therein, gating means responsive to said key depressions to effect a binary one count in said counter, and logic gating means responsive to a count in said counter other than said binary zero count to gate said clock pulses to said read-only memory means and to the input of said counter, whereby 2N-1 clock pulses are applied to said read-only memory in response to each of said key depressions.

Claim 2

Dependent Claim 383 words

A binary code transmission system comprising a keyboard means including a plurality of key members, each of said key members being selectively depressable to one of a plurality of positions to select each of an assigned plurality of characters to be transmitted, a read-only memory means including means to store an assigned multi-bit code word therein for each of said plurality of characters to be transmitted, addressing means responsive to each depression of said key members to effect readout of the stored multi-bit code word assigned to that key depression, transmitter means including a transmitter modulator means, control means responsive to said keyboard depressions to activate said transmitter means, said transmitter modulator means receiving said stored code word readout from said read-only memory and developing in response thereto a corresponding modulating waveform, said transmitter means being responsive to said modulating waveform to transmit a carrier wave signal modulated in accordance therewith, said control means including means responsive to the completion of the readout of the last bit of predetermined coded message addressed from said read-only memory to deactivate said transmitter means; said control means comprising a source of clock pulses, logic means receiving said clock pulses and being responsive to said keyboard depressions to apply said clock pulses to said read-only memory to effect a serial readout from said read-only memory of said multi-bit code word assigned to that key depression, said read out being effected at a rate defined by said clock pulses, and said logic means comprising means to inhibit application of said clock pulses to said read-only memory upon application thereto of a number of clock pulses corresponding in number to the number of bits comprising each said multi-bit code word; said multi-bit code words comprising a plurality of 2N-1 bits each, said logic means comprising an N bit continuous binary counter having a rest state exhibiting a binary zero count therein, gating means responsive to said key depressions to effect a binary one count in said counter, and logic gating means responsive to a count in said counter other than said binary zero count to gate said clock pulses to said read-only memory means and to the input of said counter, whereby 2N-1 clock pulses are applied to said read-only memory in response to each of said key depressions.

Claim 3

Dependent Claim 147 words

A transmitting system as defined in claim 1 wherein each said key depression generates a binary one logic level, means for applying said binary one logic level to said logic means, said logic means comprising an AND gate receiving said clock pulses and key depression generated binary one logic level as respective first and second inputs thereto, an OR gating means receiving the respective bit outputs of said N bit counter, the output of said OR gating means applied as a third input to said AND gate, a further OR gating means receiving said key depression generated binary one logic level, and the output of said AND gate as respective inputs thereto, the output of said further OR gating means being applied as input to said binary counter, and the output of said AND gate comprising 2N-1 consecutive clock pulses for application to said read-only memory means.

Claim 4

Dependent Claim 97 words

A transmitting system as defined in claim 2 wherein said read-only memory means comprises a shift register having a plurality of 2N-1 stages, the output of said AND gate being applied as a shift input to said shift register, means responsive to each said key depression to set into the respective stages of said shift register successive binary code word bits assigned to that key depression, the output stage of said shift register exhibiting a serial read out of said stored binary code word upon application of said train of 2N-1 clock pulses to said shift register.

Claim 5

Dependent Claim 136 words

A transmitting system as defined in claim 3 wherein said multi-bit code words comprise teleprinter start-stop code words each comprising a start bit followed sequentially by five character defining bits and terminated by a stop bit, said multi-bit counter comprising a three-bit counter, means responsive to said key depression binary one logic generations to effect predetermined set and reset functions of the first five stages of said shift register to the five character defining bits assigned to each selected character to be transmitted, and means responsive to said three-bit counter exhibiting a count transition from 111 to 000 to set the output stage of said shift register to a predetermined binary level corresponding to said stop bit and the next preceding stage of said shift register to a predetermined binary level corresponding to said start bit.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-11-12	1977-05-14	1977-11-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-11-12	1981-05-14	1981-11-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-11-12	1985-05-14	1985-11-13	$7700.00	Window Closed / Lapsed

Code transmission system

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