Course difference logic for use with digital magnetic compass

Claim 2

For use with a compass providing Gray coded signals representative of compass headings, logic circuitry operative in response to said signals to provide an output indication of course difference comprising: converter means for converting said signals to binary coded signals representing a binary code which is the complement of the binary equivalent of a received Gray code from said compass; first unidirectional binary counter means; means for presetting said first counter means with a binary number representative of an actual course sensed by said compass; first clock means for providing first clock pulses to increment said first counter means from said preset binary number to a predetermined count; first decoder means coupled to the output of said first counter means and operative in response to said predetermined count to provide an output signal operative to stop operation of said first clock means; said first clock pulses being of a number representative of actual compass heading; second unidirectional binary counter means; means for presetting said second counter means with a binary number representative of an intended course; second clock means for providing second clock pulses to increment said second counter means for the number entered therein to a predetermined count; second decoder means operative in response to the predetermined count from said second couNter means to provide an output signal operative to stop provision of said second clock pulses; and logic circuit means operative in response to said first and said second clock pulses to provide course difference output pulses of a number representative of the difference between said actual and intended courses; said output signal from said second decoder means being of a value during production of said course difference pulses representative of the sense of course difference.

Claim 3

For use with a compass providing Gray coded signals representative of compass headings, logic circuitry operative in response to said signals to provide an output indication of course difference comprising: converter means for converting said signals to binary coded signals representing a binary code which is the complement of the binary equivalent of a received Gray code from said compass; a first unidirectional binary counter receiving the binary output signals from said converter means; first decoder means coupled to the output of said counter and operative to provide an output signal in response to a predetermined count therefrom; first clock means for providing clock pulses to increment said counter from the binary number entered therein to a predetermined higher count at which said first decoder means is responsive; said decoder output signal being operative to stop operation of said first clock means; the clock pulses provided by said first clock means being of a number representative of an actual compass course; means for providing a binary signal representation of an intended course; a second unidirectional binary counter receiving the binary signals from said intended course means; second decoder means coupled to the output of said second counter and operative to provide an output signal in response to a predetermined count therefrom; pulse detector means operative in response to the clock pulses from said first clock means to provide a load signal to said second counter and an enable signal; second clock means enabled by said enable signal and operative in response to the clock pulses from said first clock means to provide corresponding clock pulses for said second counter and also operative in the absence of received clock pulses from said first clock means to provide clock pulses for said second counter so long as said enable signal is present; first gate means receiving the clock pulses from said second clock means and the output signal from said second decoder means and operative to apply clock pulses to said second counter means; second gate means receiving the clock pulses from said first clock means and from said first gate means and operative to provide output pulses of a number representative of the difference between said actual and intended courses; the output signal from said second decoder means having a binary value during the production of said course difference pulses representative of the sense of course difference.

Claim 4

For use with a compass providing Gray coded signals representative of compass headings, logic circuitry operative in response to said signals to provide an output indication of course difference comprising: converter means for converting said signals to binary coded signals representing a binary code which is the complement of the binary equivalent of a received Gray code from said compass; a first unidirectional binary counter receiving the binary output signals from said converter means; first decoder means coupled to the output of said counter and operative to provide an output signal in response to a predetermined count therefrom; first clock means for providing clock pulses to increment said counter from the binary number entered therein to a predetermined higher count at which said first decoder means is responsive; said decoder output signal being operative to stop operation of said first clock means; the clock pulses provided by said first clock means being of a number representative of an actual compass course; means for providing a binary signal representation of an intended course; a second unidirectional binary counter receiving the binary signals from said intended course means; second decoder means coupled to the output of said second counter and operative to provide an output signal in response to a predetermined count therefrom; pulse detector means operative in response to the clock pulses from said first clock means to provide a load signal to said second counter and an enable signal; second clock means enabled by said enable signal and operative in response to the clock pulses from said first clock means to provide corresponding clock pulses for said second counter and also operative in the absence of received clock pulses from said first clock means to provide clock pulses for said second counter so long as said enable signal is present; first gate means receiving the clock pulses from said second clock means and the output signal from said second decoder means and operative to apply clock pulses to said second counter means; second gate means receiving the clock pulses from said first clock means and from said first gate means and operative to provide output pulses of a number representative of the difference between said actual and intended courses; the output signal from said second decoder means having a binary value during the production of said course difference pulses representative of the sense of course difference.

Claim 5

The invention according to claim 2 wherein said Gray coded signals represent a selected code sequence of Gray coded values which provide unambiguous transition throughout the compass circle.

Claim 6

Theinvention according to claim 2 wherein said Gray coded signals represent a sequence of Gray coded values corresponding to decimal numbers from 76 to 435, The invention the Gray coded equivalent of decimal 76 representing a compass heading of 0*, the Gray coded equivalent of decimal 435 representing a compass heading of 359*.

Claim 7

The invention according to claim 2 wherein said converter means includes: a Gray-to-binary converter; and means for inverting the signal representing the most significant bit of said Gray code prior to application of said bit to said Gray-to-binary converter.

Claim 8

The invention according to claim 2 wherein said first clock means includes; a first clock operative at a predeteRmined rate for providing said clock pulses; and a slow clock operative at a predetermined lower rate than the rate of said first clock and operative to control the sampling rate at which signals are processed.

Claim 9

The invention according to claim 5 wherein said second clock means includes: a triggered clock circuit operative in the presence of said enable signal to provide clock pulses at a predetermined rate, and operative in the presence of said enable signal and clock pulses received from said first clock means to provide clock pulses at a faster rate equal to the rate of said received clock pulses.

Claim 10

The invention according to claim 7 wherein said pulse detector means includes: a pulse train detector operative to provide said load and enable signals for the duration of the clock signals received from said first clock means and for a predetermined further interval sufficient to permit processing of the greatest possible course difference.

Claim 11

The invention according to claim 8 wherein said second gate means includes: an exclusive OR gate operative to provide an output pulse only in the presence of either a clock pulse from said first clock means or said first gate means, thereby to provide said output pulses of a number representative of course difference.

Claim 12

The invention according to claim 9 wherein said first gate means includes: a AND gate operative in the presence of an output signal from said second decoder means of first binary level to apply clock pulses to said second counter means and said second gate means.