3d-coaxial memory construction and method of making

Claim 1

In a method of making a stacked multi-wafer digital memory, the steps of: providing a plurality of conductive wafers, selectively removing material from opposite surfaces of each wafer and replacing at least a portion of the removed material with dielectric material so as to form a plurality of spaced electrically insulated Z-axis through-terminals in each wafer supported therein and electrically insulated therefrom by said dielectric material and with at least predetermined ones of said Z-axis terminals being formed as through-terminals located in a like predetermined pattern in each wafer so that respective through-terminals will be aligned when the wafers are stacked, forming a pressure-deformable contact of material more malleable than said wafers on at least one end of each Z-axis throughterminal so that said contact is provided between each aligned pair or Z-axis through-terminals on adjacent wafers when the wafers are stacked, mounting and electrically connecting memory element chips each having a plurality of output leads to predetermined ones of said wafers in a like predetermined manner on each wafer with a majority of the output leads of each chip being electrically connected to respective Z-axis through-terminals of its respective wafer, and stacking said wafers under pressure sufficient to deform said pressure-deformable contacts and thereby form a plurality of insulated coaxially shielded Z-axis conductive paths within the stack electrically interconnecting respective ones of said majority of output leads of said chips.