Switched oscillator clock pulse generator

Claim 2

A clock pulse generating system comprising: a plurality of output transmission means; a corresponding plurality of signal generators; master selection means for selecting one of said plurality of signal generators as master generator; means for phase locking the remainder of said plurality of signal generators to signals generated by the generator selected as master; output selection means for applying selectively to each of said transmission means corresponding to said remainder of said plurality of signal generators signals generated by said corresponding signal generator and said signals generated by said master generator and for applying output signals of said master generator to said transmission means corresponding thereto.

Claim 3

A clock pulse generating system in accordance with claim 1 and further comprising: an external source of reference signals and means for phase locking the signal generator selected as master to said reference signals.

Claim 4

A clock pulse generating system comprising: a plurality of output transmission means; a plurality of signal generators equal in number to said plurality of output transmission means and corresponding on a one-for-one basis therewith; fault detection means coupled to said signal generators for generating selection control signals defining the operating states of said signal generators in said clock pulse generating system; master selection means connected to said fault detection means and responsive to said selection control signals for selecting one of said signal generators as a master generator and for generating corresponding master control signals; means for phase locking the remainder of said plurality of signal generators to signals generated by said selected master generator; and output selection means responsive to said master control signals for applying selectively signals from said corresponding signal generator and from said master generator to each of said transmission means corresponding to said remainder of said plurality of signal generators and for applying signals from said master generator to said transmission means corresponding thereto.

Claim 5

A clock pulse generating system comprising: a plurality of output transmission means; a plurality of signal generators equal in number to said plurality of output transmission means and corresponding on a one-for-one basis therewith; fault detection means coupled to said signal generators for generating selection control signals defining the operating states of said signal generators in said clock pulse generating system; master selection means connected to said fault detection means and responsive to said selection control signals for selecting one of said signal generators as a master generator and for generating corresponding master control signals; means for phase locking the remainder of said plurality of signal generators to signals generated by said selected master generator; and output selection means responsive to said master control signals for applying selectively signals from said corresponding signal generator and from said master generator to each of said transmission means corresponding to said remainder of said plurality of signal generators and for applying signals from said master generator to said transmission means corresponding thereto.

Claim 6

The system in accordance with claim 3 wherein said plurality of signal generators are individually preferred as master signal generator in an ordered sequence, said master selection means comprises: bistable means having first and second stable states, means for controlling the states of said bistaBle means, and said master selection means comprises means responsive to said selection control signals and to output signals of said bistable means for selecting the next signal generator in the ordered sequence indicated to be trouble free by said selection control signals as said master signal generator upon the occurrence of an indicated error in the operation of the current master generator.

Claim 7

A clock pulse generating system comprising: a plurality of circuit means each comprising a local signal generator, reference signal input terminals, means for phase locking the local signal generator to signals applied to said reference signal input terminals, error detection circuits, output terminals, and output selection means responsive to signals generated by said error detection circuits to selectively apply signals appearing on said reference signal input terminals and signals generated by said local signal generator to said output terminals; master selector means responsive to signals generated by the error detection circuits of said plurality of circuit means to selectively designate one of said plurality of circuit means as master and to apply signals generated by the local signal generator of the circuit means designated as master to the reference signal input terminals of the other circuit means of said plurality of circuit means.

Claim 8

A clock pulse generating system comprising: a plurality of circuit means each comprising a local signal generator, reference signal input terminals, means for phase locking the local signal generator to signals applied to said reference signal input terminals, error detection circuits, output terminals, and output selection means responsive to signals generated by said error detection circuits to selectively apply signals appearing on said reference signal input terminals and signals generated by said local signal generator to said output terminals; master selector means responsive to signals generated by the error detection circuits of said plurality of circuit means to selectively designate one of said plurality of circuit means as master and to apply signals generated by the local signal generator of the circuit means designated as master to the reference signal input terminals of the other circuit means of said plurality of circuit means.

Claim 9

A clock pulse generating system in accordance with claim 5 wherein said error detection circuits include level detection circuits which generate level error signals when certain signals fall below a preset level; and wherein said master selector means comprises means for designating as master a first one of said circuit means in the absence of any error signals from the error detection circuits of said first circuit means, and responsive to a level error signal generated by said first circuit means to designate as master a next circuit means in which no level error has occurred.

Claim 10

A clock pulse generating system in accordance with claim 5 wherein said plurality of circuit means comprises at least three of said circuit means; wherein said error detection circuits include circuits which detect phase difference between certain signals and a reference signal to generate phase error signals; and wherein said master selector means comprises means for designating as master a first one of said circuit means, and responsive to phase error signals generated by any two of said other circuit means to designate one of said other circuit means as master.

Claim 11

A clock pulse generating system in accordance with claim 5 and further comprising selector means connected to the output terminals of a first, and a second of said plurality of circuit means and comprising signal level error detection circuits for selectively applying signals from the output terminals of said first and second circuit means to a first output transmission means; and selector means connected to the output terminals of a third and a fourth of said plurality of circuit means and comprising signal level error detection circuits for selectively applying signals from the output terminals of said third and fourth circuit means to a second output transmission means.

Claim 12

A clock pulse generating system in accordance with claim 8 and further comprising: selector means connected to said first and said second output transmission means, and comprising signal level error detection means for applying selectively signals from said first and said second output transmission means to a third output transmission means.

Claim 13

A clock pulse generating system comprising: a plurality of output transmission means; a plurality of signal generators; master selection means for selecting one of said plurality of signal generators as master generator in accordance with a plan wherein said plurality of signal generators are individually preferred as master signal generator in an ordered sequence; and means for deriving output signals from signalS generated by said master generator and applying said output signals to said output transmission means; said master selection means comprises: means corresponding in number to said plurality of signal generators and coupled to said signal generators for generating selection control signals defining the operating states of said signal generators in said clock pulse generating system, bistable means having first and second stable states, means for controlling the states of said bistable means, and means responsive to said error signals and to output signals of said bistable means for selecting the next signal generator in the ordered sequence indicated to be trouble free as said master signal generator.

Claim 14

A clock pulse generating system comprising: a plurality of output transmission means; a plurality of signal generators; master selection means for selecting one of said plurality of signal generators as master generator in accordance with a plan wherein said plurality of signal generators are individually preferred as master signal generator in an ordered sequence; and means for deriving output signals from signalS generated by said master generator and applying said output signals to said output transmission means; said master selection means comprises: means corresponding in number to said plurality of signal generators and coupled to said signal generators for generating selection control signals defining the operating states of said signal generators in said clock pulse generating system, bistable means having first and second stable states, means for controlling the states of said bistable means, and means responsive to said error signals and to output signals of said bistable means for selecting the next signal generator in the ordered sequence indicated to be trouble free as said master signal generator.