Patent US3769593A successfully refreshed from Google Patents.
US3769593A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Battery conservation circuit
Assignee: Stewart Warner Corp
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Filing: 1972-03-08
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Granted: 1973-10-30
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Expires: 1992-03-08
Abstract
Abstract A battery conservation circuit for a selective paging receiver adapted to receive subscriber address-bearing code signals of a specific format comprises a timing circuit which periodically energizes the receiver for short periods of time to determine if valid address-bearing signals having the specific format are present. If such signals are present, the timer is latched in the on state and the receiver is continuously energized to permit decoding received addresses. When valid signals are no longer present, or when the amplitude of the reserved signal is too low for reliable operation, the timer circuit is unlatched after a predetermined time delay to resume the battery-saving cycle.
Inventors
- 👤 R Williams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:58
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0225; H04W52/0229; G; G08; G08B; G08B3/00; G08B3/10; G08B3/1008; G08B3/1016; G08B3/1025; G08B3/1066; H04W88/00; H04W88/02; H04W88/022; H04W88/025; H04W88/028; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
642 words
In a portable selective paging receiver of the type operated by an internal battery for detecting a cyclically repeated subscriber address-bearing signal of a predetermined format, a battery conservation circuit comprising; a first inverter amplifier having input and output terminals; means connected to the output terminal of said first amplifier for rendering said battery effective to operate said receiver for detecting said subscriber signal only in response to said first amplifier providing one output signal and rendering said battery ineffective to operate said receiver in response to said amplifier providing another output signal; a logic gate having a pair of input terminals and an output terminal coupled to the input terminal of said first inverter amplifier for providing one control signal for controlling said first amplifier to provide said one output signal only in response to one predetermined input signal Applied to either one or both of said gate input terminals and providing another control signal for controlling said first amplifier to provide said other output signal in response to another predetermined input signal applied to both said gate input terminals; second inverter amplifier means having input and output means with said second amplifier means output means coupled to one input terminal of said logic gate for providing either said one or other predetermined input signals to said gate one input terminal; a capacitor connected between said first amplifier output terminal and said second inverter amplifier input means with said first amplifier supplying said capacitor with a respective reference voltage corresponding respectively to said one and other first amplifier output signal; a pair of parallel resistors with one of said resistors being of low value relative the other resistor and having a unidirectional circuit element in series therewith to charge said capacitor in one direction through said one resistor and unidirectional element against one reference voltage in a relatively short time period in response to said logic gate providing said one control signal to said first amplifier whereby said second amplifier is controlled to terminate said one predetermined input signal and apply said other input signal to terminate said gate one control signal and operation of said receiver whereafter said gate other control signal charges said capacitor in the opposite direction through the other resistor of said pair against another reference voltage in a relatively long period whereby said second amplifier is controlled to terminate said other input signal and apply said one input signal for providing said gate one control signal to render said battery effective to operate said receiver; a transistor having a base circuit and an emitter circuit connected to the other input terminal of said logic gate; an RC circuit including a resistor and series capacitor connected across said battery with the junction of said RC circuit serially connected resistor and capacitor connected to said base circuit; a counter producing a control signal of a predetermined direction in response to each detection of said address-bearing signal of said predetermined format during the period said battery is effective to operate said receiver; a unidirectional circuit element biased in one direction connected to the juncture of said RC circuit serially connected resistor and capacitor to prevent the charging of said capacitor and hold said transistor nonconductive and biased in the reverse direction in response to the production of said counter control signal of predetermined direction to enable said RC circuit capacitor to charge to a value for rendering said transistor conductive to provide said one predetermined input signal to said gate other input terminal; and means rendered effective in response to the conduction of said transistor for maintaining said one predetermined input signal at said gate other input terminal for a last period longer than the cyclic repetition of said address-bearing signal to control said first amplifier to render said battery effective to operate said receiver for said last period.
Claim 2
Dependent Claim
642 words
In a portable selective paging receiver of the type operated by an internal battery for detecting a cyclically repeated subscriber address-bearing signal of a predetermined format, a battery conservation circuit comprising; a first inverter amplifier having input and output terminals; means connected to the output terminal of said first amplifier for rendering said battery effective to operate said receiver for detecting said subscriber signal only in response to said first amplifier providing one output signal and rendering said battery ineffective to operate said receiver in response to said amplifier providing another output signal; a logic gate having a pair of input terminals and an output terminal coupled to the input terminal of said first inverter amplifier for providing one control signal for controlling said first amplifier to provide said one output signal only in response to one predetermined input signal Applied to either one or both of said gate input terminals and providing another control signal for controlling said first amplifier to provide said other output signal in response to another predetermined input signal applied to both said gate input terminals; second inverter amplifier means having input and output means with said second amplifier means output means coupled to one input terminal of said logic gate for providing either said one or other predetermined input signals to said gate one input terminal; a capacitor connected between said first amplifier output terminal and said second inverter amplifier input means with said first amplifier supplying said capacitor with a respective reference voltage corresponding respectively to said one and other first amplifier output signal; a pair of parallel resistors with one of said resistors being of low value relative the other resistor and having a unidirectional circuit element in series therewith to charge said capacitor in one direction through said one resistor and unidirectional element against one reference voltage in a relatively short time period in response to said logic gate providing said one control signal to said first amplifier whereby said second amplifier is controlled to terminate said one predetermined input signal and apply said other input signal to terminate said gate one control signal and operation of said receiver whereafter said gate other control signal charges said capacitor in the opposite direction through the other resistor of said pair against another reference voltage in a relatively long period whereby said second amplifier is controlled to terminate said other input signal and apply said one input signal for providing said gate one control signal to render said battery effective to operate said receiver; a transistor having a base circuit and an emitter circuit connected to the other input terminal of said logic gate; an RC circuit including a resistor and series capacitor connected across said battery with the junction of said RC circuit serially connected resistor and capacitor connected to said base circuit; a counter producing a control signal of a predetermined direction in response to each detection of said address-bearing signal of said predetermined format during the period said battery is effective to operate said receiver; a unidirectional circuit element biased in one direction connected to the juncture of said RC circuit serially connected resistor and capacitor to prevent the charging of said capacitor and hold said transistor nonconductive and biased in the reverse direction in response to the production of said counter control signal of predetermined direction to enable said RC circuit capacitor to charge to a value for rendering said transistor conductive to provide said one predetermined input signal to said gate other input terminal; and means rendered effective in response to the conduction of said transistor for maintaining said one predetermined input signal at said gate other input terminal for a last period longer than the cyclic repetition of said address-bearing signal to control said first amplifier to render said battery effective to operate said receiver for said last period.
Claim 3
Dependent Claim
69 words
The conservation circuit claimed in claim 1 in which said means rendered effective to maintain said one predetermined input signal at said gate other input terminal comprises a last capacitor connected to said transistor emitter circuit and said gate other input terminal and charged in one direction in response to conduction by said transistor, and a resistor providing a discharge path for said last capacitor during said last period.
Claim 4
Dependent Claim
63 words
In the conservation circuit claimed in claim 2 a last transistor having a collector circuit connected to said gate other input terminal and having a base circuit connected to the output terminal of said gate whereby said last transistor is rendered effective to rapidly discharge said last capacitor in respoNse to the initiation of a shift in the output of said logic gate.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-29 | 1977-04-30 | 1977-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-29 | 1981-04-30 | 1981-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-29 | 1985-04-30 | 1985-10-30 | $7700.00 | Window Closed / Lapsed |