Apparatus and method for converting mos circuit signals to ttl circuit signals

Claim 2

An electronic converter circuit for converting the signals from a MOSFET memory unit (a MOS circuit signal) to signals suitable for processing by TTL circuits (a TTL circuit signal) comprising: a converter network for converting said MOS circuit signal into a converter signal; a storage network coupled to said converter network for establishing and maintaining a storage signal in response to said converter signal, said storage network being enabled to respond to said converter signal by a first control signal, said storage network being enabled for maintaining said storage signal by a second control signal; and an output network coupled to said storage network, for establishing an output signal in response to said storage signal, said output network responsive to a third control signal for electronically isolating said storage signal from an output terminal of said electronic converter circuit.

Claim 3

An electronic converter circuit of claim 1 further comprising: a threshold network coupled to said converter network for converting said MOS circuit signal into said converter signal when said MOS circuit signal exceeds a threshold value.

Claim 4

The electronic converter circuit of claim 2, wherein said storage network comprises a first logic ''''NAND'''' circuit, a second logic ''''NAND'''' circuit and a third logic ''''NAND'''' circuit, said third logic ''''NAND'''' circuit coupled to said first logic ''''NAND'''' circuit, said second logic ''''NAND'''' circuit, and said output network, said first logic ''''NAND'''' gate being coupled to said converter network, said storage signal being applied to an output terminal of said third logic ''''NAND'''' gate in response to said converter signal and said first control signal being applied to input terminals of said first logic ''''NAND'''' circuit, said storage signal being maintained at said output terminal of said third logic ''''NAND'''' circuit in response to said second control signal being applied to an input terminal of said second logic ''''NAND'''' gate.

Claim 5

The electronic converter circuit of claim 3 wherein said first ''''NAND'''' circuit and said second ''''NAND'''' circuit comprise multi-emitter transistor gates and first inverting transistor amplifying pairs, and wherein said third ''''NAND'''' circuit comprises a second inverting transistor amplifying pair.

Claim 6

An electronic converter circuit for producing TTL circuit signals in response to MOS circuit signals comprising: a converter network for converting an MOS input current signal to a converter signal voltage, a storage network coupled to said converter network, wherein said storage network includes: controllable amplifying means for applying a storage signal at an output terminal of said storage network in response to said converter signal, enabling means, coupled to said amplifying means, for enabling said amplifying means in response to a first external signal, storage means, coupled to said amplifying means for maintaining said storage signal in response to a second external signal, and an output network coupled to said storage network for producing an output signal at an output terminal to said storage signal, said output network including a disable means for electrically isolating said output terminal from said storage signal in response to a third external signal.

Claim 7

An electronic converter circuit for producing TTL circuit signals in response to MOS circuit signals comprising: a converter network for converting an MOS input current signal to a converter signal voltage, a storage network coupled to said converter network, wherein said storage network includes: controllable amplifying means for applying a storage signal at an output terminal of said storage network in response to said converter signal, enabling means, coupled to said amplifying means, for enabling said amplifying means in response to a first external signal, storage means, coupled to said amplifying means for maintaining said storage signal in response to a second external signal, and an output network coupled to said storage network for producing an output signal at an output terminal to said storage signal, said output network including a disable means for electrically isolating said output terminal from said storage signal in response to a third external signal.

Claim 8

The electronic converter circuit of claim 5 further comprising: a threshold network coupled to said converter network producing a change in said converter signal voltage, when said MOS input signal exceeds a threshold value.

Claim 9

The electronic converter circuit of claim 6 wherein said first external signal is applied during a period of electrical inactivity of an MOS circuit producing said MOS input signals.

Claim 10

An electronic converter circuit for producing a TTL circuit signal in response to an MOS circuit signal from a MOS memory unit comprising: means for converting an input current signal into a converter voltage signal; means for storing said converter voltage signal coupled to said converter means and adapted to receive a first control signal, said storage means storing said converter voltage signal in response to said first control signal; means for clearing said converter voltage signal from said storage means in response to a second control signal, said storage means maintaining said converter voltage signal during an absence of said second control signal; and output means coupled to said storage means adapted to receive a third control signal, said output means establishing said TTL circuit signal at an output terminal of said output means in response to said converter voltage signal stored in said storage means, said converter voltage signal being isolated from said output terminal in response to said third control signal.

Claim 11

An electronic converter circuit for producing a TTL circuit signal in response to an MOS circuit signal from a MOS memory unit comprising: means for converting an input current signal into a converter voltage signal; means for storing said converter voltage signal coupled to said converter means and adapted to receive a first control signal, said storage means storing said converter voltage signal in response to said first control signal; means for clearing said converter voltage signal from said storage means in response to a second control signal, said storage means maintaining said converter voltage signal during an absence of said second control signal; and output means coupled to said storage means adapted to receive a third control signal, said output means establishing said TTL circuit signal at an output terminal of said output means in response to said converter voltage signal stored in said storage means, said converter voltage signal being isolated from said output terminal in response to said third control signal.

Claim 12

The electronic converter circuit of claim 8 wherein said MOS circuit signal is derived from an MOS memory cell, and wherein said first control signal is applied during a period of inactivity of said MOS memory cell.

Claim 13

The electronic converter circuit of claim 9, further comprising means for establishing a threshold signal level coupled to said converter means producing said converter voltage signal, when said input current signal exceeds a threshold value.

Claim 14

An electronic converter circuit for producing TTL circuit signals in response to MOS circuit signals comprising: a converter network including an input current threshold network and a first amplifying network, said threshold network coupled to said first amplifying network, said converter network causing an output signal of said first amplifying network in response to an input current above a specified value; a storage network including a first logic ''''NAND'''' circuit, a second logic ''''NAND'''' circuit and a third logic ''''NAND'''' circuit, said first amplifying network coupled to a first input terminal of said first ''''NAND'''' circuit, said first ''''NAND'''' circuit adapted to receive a first control signal applied to a second input terminal, wherein an output terminal of said first ''''NAND'''' circuit is coupled to a first input terminal of said second ''''NAND'''' circuit, wherein an output terminal of said third ''''NAND'''' circuit is coupled to a second input terminal of said second ''''NAND'''' circuit, wherein an output terminal of said second ''''NAND'''' circuit is coupled to a first input terminal of said third ''''NAND'''' circuit wherein said third ''''NAND'''' circuit is adapted to receive a second control voltage applied to a second input terminal, wherein a storage signal at said output terminal of said second ''''NAND'''' circuit is established in response to said output signal of said first amplifying network and said first control signal, and wherein said storage signal is maintained at said output terminal of said second ''''NAND'''' circuit in response to said second control signal; and an output network, including a switching network and a second amplifying network, said second amplifying network coupled to said switching network, said switching network coupled to said output terminal of said second ''''NAND'''' circuit wherein an output signal applied to a converter circuit output terminal by said second amplifying network in response to said storage signal, said switching network adapted to receive a third control signal, said third control signal causing said switching network to electrically isolate a signal from said converter circuit output terminal from an output terminal of said output network.

Claim 15

An electronic converter circuit for producing TTL circuit signals in response to MOS circuit signals comprising: a converter network including an input current threshold network and a first amplifying network, said threshold network coupled to said first amplifying network, said converter network causing an output signal of said first amplifying network in response to an input current above a specified value; a storage network including a first logic ''''NAND'''' circuit, a second logic ''''NAND'''' circuit and a third logic ''''NAND'''' circuit, said first amplifying network coupled to a first input terminal of said first ''''NAND'''' circuit, said first ''''NAND'''' circuit adapted to receive a first control signal applied to a second input terminal, wherein an output terminal of said first ''''NAND'''' circuit is coupled to a first input terminal of said second ''''NAND'''' circuit, wherein an output terminal of said third ''''NAND'''' circuit is coupled to a second input terminal of said second ''''NAND'''' circuit, wherein an output terminal of said second ''''NAND'''' circuit is coupled to a first input terminal of said third ''''NAND'''' circuit wherein said third ''''NAND'''' circuit is adapted to receive a second control voltage applied to a second input terminal, wherein a storage signal at said output terminal of said second ''''NAND'''' circuit is established in response to said output signal of said first amplifying network and said first control signal, and wherein said storage signal is maintained at said output terminal of said second ''''NAND'''' circuit in response to said second control signal; and an output network, including a switching network and a second amplifying network, said second amplifying network coupled to said switching network, said switching network coupled to said output terminal of said second ''''NAND'''' circuit wherein an output signal applied to a converter circuit output terminal by said second amplifying network in response to said storage signal, said switching network adapted to receive a third control signal, said third control signal causing said switching network to electrically isolate a signal from said converter circuit output terminal from an output terminal of said output network.

Claim 16

The electronic converter circuit of claim 11 wherein said first ''''NAND'''' circuit and said third ''''NAND'''' circuit are comprised of multI-emitter transistor gates and inverting transistor amplifying pairs and said second ''''NAND'''' circuit is comprised of an inverting transistor amplifying pair.

Claim 17

The electronic converter circuit of claim 12 wherein said input current threshold network comprises: a transistor coupled to an input terminal of said converter circuit, a diode coupled to said transistor, an amplifying transistor pair coupled to said transistor, said amplifying pair maintaining a voltage level at a collector of said transistor constant so long as current in said transistor is below said specified value, said current in said transistor supplied by the sum of current in said diode and current applied to said input terminal of said converter circuit.

Claim 18

The electronic converter circuit of claim 13 wherein said MOS circuit consists of a MOSFET device and wherein said input current threshold network further comprises a resistor coupled to said amplifying transistor pair, wherein thermal characteristic of said resistor and a first transistor of said amplifying transistor pair compensate thermal characteristic of said MOSFET device.

Claim 19

The electronic converter circuit of claim 14 wherein said input current threshold network causes a change in said specified value to compensate for a change of current from said MOSFET device due to variation of a power supply.