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US3767944A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Triggered bistable multivibrator circuits utilizing complenentary transistor pairs
Assignee: Texas Instruments Inc
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Filing: 1971-07-26
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Granted: 1973-10-23
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Expires: 1991-07-26
Abstract
Abstract The disclosure is directed to electronic multivibrator circuits utilizing two pairs of series connected complementary transistors, with the bases of each of the transistors being cross-coupled to the juncture point of the transistors of the opposite pair. A monostable multivibrator is provided which has the base of one of the transistors coupled through a resistance to ground potential, and includes a normally non-conductive transistor connected to receive a triggering signal for initiating a monostable timing period. A bistable multivibrator is provided which includes triggering transistors connected across symmetrical portions of the circuitry for receiving set and reset triggering signals to control the bistable operation of the circuit. A free-running multivibrator is provided which includes resistive current paths from two of the transistor bases to ground potential for generation of a periodic pulse train output upon the application of electrical power.
Inventors
- 👤 R Stehlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:17
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/282; H03K3/2823; H03K3/284
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
575 words
A triggered bistable multivibrator having a preselected bistable timing period, comprising in combination: first and second conductors adapted to be respectively connected to first and second voltage sources; a first normally conducting transistor of one conductivity type having a collector, emitter and base and a second normally nonconducting transistor of opposite conductivity type having a collector, emitter and base, and first and second transistors being connected in series in a common collector configuration with their emitters being respectively connected to said first and second conductors; a third normally non-conducting transistor of said one conductivity type having a collector, emitter and base and a fourth normally conducting transistor of said opposite conductivity type having a collector, emitter and base, said third and fourth transistors being connected in series in a common collector configuration with their emitters being respectively connected to said first and second conductors; first and second output means, said first output means being connected to the common collectors of said first and second transistors, and said second output means being connected to the common collectors of said third and fourth transistors; a first pair of RC circuits, each of said first pair of RC circuits including a capacitor and a resistor connected in series, one of said first pair of RC circuits being coupled to said first output means and the other of said first pair of RC circuits being coupled to said second output means; the bases of said third and fourth transistors being respectively coupled to said first and second output means through said one and said other of said first pair of RC circuits; a second pair of RC circuits, each of said second pair of RC circuits including a capacitor and a resistor connected in parallel, one of said second pair of RC circuits being coupled to said first output means and the other of said second pair of RC circuits being coupled to said second output means; the bases of said fourth and second transistors being respectively coupled to said first and second output means through said one and said other of said second pair of RC circuits; first and second input transistors of said opposite conductivity type, each having a collector, emitter and base with the emitters thereof being connected to said second conductor, the collector of said first input transistor being connected to a junction terminal between the capacitor and the resistor of said other of saId first pair of RC circuits interposed between the base of said first transistor and said second output means, and the collector of said second input transistor being connected to a junction terminal between the capacitor and the resistor of said one of said first pair of RC circuits interposed between the base of said third transistor and said first output means; first and second resistors respectively included in the input lines to said first and second input transistors; and said first and fourth transistors being conductive while said second and third transistors are non-conductive in a first stable conductive state of the multivibrator in response to the input of a trigger signal through said first resistor to said first input transistor, and said second and third transistors being conductive while said first and fourth transistors are non-conductive in a second stable conductive state of the multivibrator in response to the input of a trigger signal through said second resistor to said second input transistor, thereby providing triggered bistable multivibrator operation.
Claim 2
Dependent Claim
575 words
A triggered bistable multivibrator having a preselected bistable timing period, comprising in combination: first and second conductors adapted to be respectively connected to first and second voltage sources; a first normally conducting transistor of one conductivity type having a collector, emitter and base and a second normally nonconducting transistor of opposite conductivity type having a collector, emitter and base, and first and second transistors being connected in series in a common collector configuration with their emitters being respectively connected to said first and second conductors; a third normally non-conducting transistor of said one conductivity type having a collector, emitter and base and a fourth normally conducting transistor of said opposite conductivity type having a collector, emitter and base, said third and fourth transistors being connected in series in a common collector configuration with their emitters being respectively connected to said first and second conductors; first and second output means, said first output means being connected to the common collectors of said first and second transistors, and said second output means being connected to the common collectors of said third and fourth transistors; a first pair of RC circuits, each of said first pair of RC circuits including a capacitor and a resistor connected in series, one of said first pair of RC circuits being coupled to said first output means and the other of said first pair of RC circuits being coupled to said second output means; the bases of said third and fourth transistors being respectively coupled to said first and second output means through said one and said other of said first pair of RC circuits; a second pair of RC circuits, each of said second pair of RC circuits including a capacitor and a resistor connected in parallel, one of said second pair of RC circuits being coupled to said first output means and the other of said second pair of RC circuits being coupled to said second output means; the bases of said fourth and second transistors being respectively coupled to said first and second output means through said one and said other of said second pair of RC circuits; first and second input transistors of said opposite conductivity type, each having a collector, emitter and base with the emitters thereof being connected to said second conductor, the collector of said first input transistor being connected to a junction terminal between the capacitor and the resistor of said other of saId first pair of RC circuits interposed between the base of said first transistor and said second output means, and the collector of said second input transistor being connected to a junction terminal between the capacitor and the resistor of said one of said first pair of RC circuits interposed between the base of said third transistor and said first output means; first and second resistors respectively included in the input lines to said first and second input transistors; and said first and fourth transistors being conductive while said second and third transistors are non-conductive in a first stable conductive state of the multivibrator in response to the input of a trigger signal through said first resistor to said first input transistor, and said second and third transistors being conductive while said first and fourth transistors are non-conductive in a second stable conductive state of the multivibrator in response to the input of a trigger signal through said second resistor to said second input transistor, thereby providing triggered bistable multivibrator operation.
Claim 3
Dependent Claim
61 words
A triggered bistable multivibrator as set forth in claim 1, further including a pair of resistors respectively connected in parallel to said one and said other of said first pair of RC circuits, and said bases of said third and first transistors being also coupled to said first and second output means through a corresponding one of said pair of resistors.
Claim 4
Dependent Claim
24 words
A triggered bistable multivibrator as set forth in claim 1 wherein said one conductivity type is PNP and said opposite conductivity type is NPN.
Claim 5
Dependent Claim
30 words
A triggered bistable multivibrator as set forth in claim 1 wherein said first and second transistors are matched complementary transistors and said third and fourth transistors are matched complementary transistors.
Claim 6
Dependent Claim
24 words
A triggered bistable multivibrator as set forth in claim 1 wherein said first voltage source is positive and said second voltage source is ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |