US3767938A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Zero sense after peak detection circuit
Assignee: International Business Machines Corp
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Filing: 1972-05-26
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Granted: 1973-10-23
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Expires: 1992-05-26
Abstract
Abstract A zero sense after peak detection circuit for rejecting noise signals includes a peak detect and hold circuit which resets a latch only if the input signal has exceeded a predetermined negative threshold voltage which is a fixed percentage of a valid signal. After the input signal exceeds the predetermined negative threshold voltage and the latch is reset, the latch is then set when a zero sense circuit senses the input signal crossing zero.
Inventors
- 👤 T Kueper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:57
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/153; G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; H03K5/1536
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
197 words
A discriminator circuit comprising an input terminal for receiving periodic time varying input signals having excursions through zero volts, first means connected to said input terminal and responsive to a time varying input signal having a predetermined peak amplitude for setting and holding a threshold level at a predetermined percentage of said peak amplitude of said time varying input signal and generating an output signal when the peak amplitude of other time varying input signals exceeds said threshold level, second means connected to said input terminal for generating a signal in response to an input signal passing through zero volts, and bistable indicating means having one input connected to receive an output signal from said first means so as to be set in one state and a second input connected to receive an output signal from said second means to be set in another state whereby said bistable indicating means is set to said one state only when an other input signal exceeds said threshold level held by said first means and set to said another state after having been seT to said one state when said second means detects said input signal passing through zero volts.
Claim 2
Dependent Claim
197 words
A discriminator circuit comprising an input terminal for receiving periodic time varying input signals having excursions through zero volts, first means connected to said input terminal and responsive to a time varying input signal having a predetermined peak amplitude for setting and holding a threshold level at a predetermined percentage of said peak amplitude of said time varying input signal and generating an output signal when the peak amplitude of other time varying input signals exceeds said threshold level, second means connected to said input terminal for generating a signal in response to an input signal passing through zero volts, and bistable indicating means having one input connected to receive an output signal from said first means so as to be set in one state and a second input connected to receive an output signal from said second means to be set in another state whereby said bistable indicating means is set to said one state only when an other input signal exceeds said threshold level held by said first means and set to said another state after having been seT to said one state when said second means detects said input signal passing through zero volts.
Claim 3
Dependent Claim
14 words
The discriminator circuit of claim 1 wherein said bistable indicating means is a latch.
Claim 4
Dependent Claim
23 words
The discriminator circuit of claim 1 wherein said threshold level is substantially 65 per cent of the peak amplitude of an input signal.
Claim 5
Dependent Claim
28 words
The discriminator circuit of claim 1 wherein said first means sets and holds a threshold level at a predetermined percentage of the negative peak of an input signal.
Claim 6
Dependent Claim
65 words
The discriminator circuit of claim 1 wherein said first means comprises a capacitor, a unidirectional charging circuit connected to said capacitor, and a discharge circuit connected to said capacitor whereby an input signal charges said capacitor as said input signal makes an excursion in one direction and after said input signal reaches a peak in said one direction said capacitor discharges to said threshold level.
Claim 7
Dependent Claim
41 words
The discriminator circuit of claim 5 wherein said unidirectional charging circuit comprises first and second emitter followers, a first diode connected between said first and second emitter followers, and a second diode connected between said second emitter follower and said capacitor.
Claim 8
Dependent Claim
20 words
The discriminator circuit of claim 5 wherein said discharge circuit comprises a resistor connected between said capacitor and ground potential.
Claim 9
Dependent Claim
18 words
The discriminator circuit of claim 1 wherein said second means comprises a differential comparator referenced to ground potential.
Claim 10
Dependent Claim
44 words
The discriminator circuit of claim 2 wherein said latch comprises first and second transistors with the collector of the first transistor connected to the base of said second transistor and the collector of the second transistor connected to the base of said first transistor.
References Cited (Backward Citations)
US3659208A
Cited
US3639779A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-22 | 1977-04-23 | 1977-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-22 | 1981-04-23 | 1981-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-22 | 1985-04-23 | 1985-10-23 | $7700.00 | Window Closed / Lapsed |