US3639779A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Limiter circuit with enable function
Assignee: GTE Sylvania Inc
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Filing: 1971-03-15
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Granted: 1972-02-01
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Expires: 1991-03-15
Abstract
Abstract A limiter circuit employing two high-gain differential voltage comparators. A positive reference voltage is established at the noninverting input of one comparator and a reference voltage of ground is established at the inverting input of the other. Input signals are applied at the inverting input of the one comparator and at the noninverting input of the other. The output of the one comparator is connected to an input of a flip-flop composed of two cross-connected NAND gates. The output of the other comparator is connected through an inverter circuit and a triggering circuit to another input of the flip-flop. The output of the flip-flop and the output of the inverter circuit are connected to an output NAND gate. The flip-flop is set by the action of the one comparator when a positive-going input signal exceeds the threshold of the positive reference voltage, thus enabling the output NAND gate. Subsequent passing of the negative-going input signal through the zero voltage threshold causes the output NAND gate to switch producing a square-wave output. This negative-going signal also causes the triggering circuit to reset the flip-flop.
Inventors
- 👤 Kenneth A Garrigus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:22
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/12; H03K5/08; H03K5/153; H03K5/1536
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
563 words
A limiter circuit including in combination a first differential amplifier having first and second input terminals and an output terminal, said first differential amplifier being operable to provide a first output condition at the output terminal in response to a voltage differential of one polarity between the first and second input terminals and being operable to produce a second output condition at the output terminal in response to a voltage differential of the opposite polarity between the first and second input terminals; a second differential amplifier having first and second input terminals and an output terminal, said second differential amplifier being operable to provide a first output condition at the output terminal in response to a voltage differential of one polarity between the first and second input terminals and being operable to produce a second output condition at the output terminal in response to a voltage differential of the opposite polarity between the first and second input terminals; first voltage reference means connected to the first input terminal of the first differential amplifier for providing a first reference voltage of the one polarity at said terminal; second voltage reference means connected to the second input terminal of the second differential amplifier for providing a second reference voltage at said terminal, said second reference voltage being of the opposite polarity with respect to said first reference voltage; a signal input terminal connected to the second input terminal of the first differential amplifier and the first input terminal of the second differential amplifier; bistable circuit means having a first operating state during which a first output condition is produced at its output terminal and a second operating state during which a second output condition is produced at its output terminal, said bistable circuit means being connected to the output terminal of the first differential amplifier and being operable to switch from the second operating state to the first operating state in response to the output condition at the output terminal of the first differential amplifier changing from the first condition to the second condition; triggering means coupled to the output terminal of the second differential amplifier and to the bistable circuit means and operable to switch the bistable circuit means from the first operating state to the second operating state in response to the output condition at the output terminal of the second differential amplifier changing from the second condition to the first condition; and output means coupled to the output terminal of the bistable circuit means and the output terminal of the second differential amplifier and having an output terminal, said output means being operable to produce a first output condition at the output terminal when the first condition is present at the output terminal of the second differential amplifier and being operable to produce a second output condition at the output terminal when the second condition is present at the output terminal of the second differential amplifier and the bistable circuit means is in the first operating state; whereby when an increasing voltage of the one polarity at the signal input terminal exceeds the first reference voltage, the bistable circuit means switches to the first operating state and subsequently when the voltage at the signal input terminal becomes of the opposite polarity with respect to the second reference voltage, the second output condition is produced at the output terminal of the output means.
Claim 2
Dependent Claim
563 words
A limiter circuit including in combination a first differential amplifier having first and second input terminals and an output terminal, said first differential amplifier being operable to provide a first output condition at the output terminal in response to a voltage differential of one polarity between the first and second input terminals and being operable to produce a second output condition at the output terminal in response to a voltage differential of the opposite polarity between the first and second input terminals; a second differential amplifier having first and second input terminals and an output terminal, said second differential amplifier being operable to provide a first output condition at the output terminal in response to a voltage differential of one polarity between the first and second input terminals and being operable to produce a second output condition at the output terminal in response to a voltage differential of the opposite polarity between the first and second input terminals; first voltage reference means connected to the first input terminal of the first differential amplifier for providing a first reference voltage of the one polarity at said terminal; second voltage reference means connected to the second input terminal of the second differential amplifier for providing a second reference voltage at said terminal, said second reference voltage being of the opposite polarity with respect to said first reference voltage; a signal input terminal connected to the second input terminal of the first differential amplifier and the first input terminal of the second differential amplifier; bistable circuit means having a first operating state during which a first output condition is produced at its output terminal and a second operating state during which a second output condition is produced at its output terminal, said bistable circuit means being connected to the output terminal of the first differential amplifier and being operable to switch from the second operating state to the first operating state in response to the output condition at the output terminal of the first differential amplifier changing from the first condition to the second condition; triggering means coupled to the output terminal of the second differential amplifier and to the bistable circuit means and operable to switch the bistable circuit means from the first operating state to the second operating state in response to the output condition at the output terminal of the second differential amplifier changing from the second condition to the first condition; and output means coupled to the output terminal of the bistable circuit means and the output terminal of the second differential amplifier and having an output terminal, said output means being operable to produce a first output condition at the output terminal when the first condition is present at the output terminal of the second differential amplifier and being operable to produce a second output condition at the output terminal when the second condition is present at the output terminal of the second differential amplifier and the bistable circuit means is in the first operating state; whereby when an increasing voltage of the one polarity at the signal input terminal exceeds the first reference voltage, the bistable circuit means switches to the first operating state and subsequently when the voltage at the signal input terminal becomes of the opposite polarity with respect to the second reference voltage, the second output condition is produced at the output terminal of the output means.
Claim 3
Dependent Claim
379 words
A limiter circuit in accordance with claim 1 wherein said bistable circuit means includes a first NAND gate having an output connection, a first input connection connected to the output terminal of the first differential amplifier, and a second input connection, said first NAND gate having a first operating condition during which a first condition is produced at its output connection and a second operating condition during which a second condition is produced at its output connection; a second NAND gate having an output connection connected to the second input connection of the first NAND gate, a first input connection connected to said triggering means, and a second input connection connected to the output connection of the first NAND gate, said second NAND gate having a first operating condition during which a first condition is produced at its output connection and a second operating condition during which a second condition is produced at its output connection; said triggering means being operable normally to produce a first condition at the first input connection of the second NAND gate and being operable momentarily to produce a second condition at the first iNput connection of the second NAND gate in response to the output condition at the output terminal of the second differential amplifier changing from the second condition to the first condition; said first NAND gate being operable in the second operating condition only when the first output condition of the first differential amplifier is present at the first input connection thereto and the first condition of the second NAND gate is present at the second input connection thereto; said second NAND gate being operable in the second operating condition only when the first output condition of the triggering means is present at the first input connection thereto and the first condition of the first NAND gate is present at the second input connection thereto; whereby said bistable circuit means is in the first operating state when the first NAND gate is in the first operating condition and the second NAND gate is in the second operating condition, and the bistable circuit means is in the second operating state when the first NAND gate is in the second operating condition and the second NAND gate is in the first operating condition.
Claim 4
Dependent Claim
64 words
A limiter circuit in accordance with claim 2 wherein said first voltage reference means includes two resistances connected in series between a source of reference voltage of the one polarity and ground; the first input terminal of the first differential amplifier is connected to the juncture of the two resistances of the first voltage reference means; and said second voltage reference means includes ground.
Claim 5
Dependent Claim
107 words
A limiter circuit in accordance with claim 3 wherein the reference voltage of the one polarity established at the first input terminal of the first differential amplifier by the first voltage reference means causes the output condition of the first differential amplifier to be changed when a voltage of the one polarity of predetermined value is present at the signal input terminal; and the reference voltage established at the second input terminal of the second differential amplifier by the second voltage reference means causes the output condition of the second differential amplifier to be changed when a zero value voltage is present at the signal input terminal.
Claim 6
Dependent Claim
217 words
A limiter circuit in accordance with claim 4 including an inverter circuit having its input connected to the output terminal of the second differential amplifier and operable to produce a first condition at its output when the second output condition is present at the output terminal of the second differential amplifier and operable to produce a second condition at its output when the first output condition is present at the output terminal of the second differential amplifier; and wherein the output means includes a NAND gate having a first input connected to the output of the first NAND gate of the bistable circuit means, a second input connected to the output of the inverter circuit, and an output connected to the output terminal of the output means; said NAND gate being operable to produce the first output condition at the output terminal of the output means when the second condition is present at the output of the first NAND gate or when the second condition is present at the output of the inverter circuit, and being operable to produce the second condition at the output terminal of the output means when the first condition is present at the output of the first NAND gate and the first condition is present at the output of the inverter circuit.
Claim 7
Dependent Claim
311 words
A limiter circuit in accordance with claim 5 wherein said one polarity is positive with respect to ground and said opposite polarity is negative with respect to ground; said first output condition at the output terminal of the first differential amplifier is a relatively high-voltage level with respect to ground and the second output condition at the output terminal of the first differential amplifier is a relatively low-voltage level with respect to ground; said first output condition at the output terminal of the second differential amplifier is a relatively high-voltage level with respect to ground and the second output condition at the output terminal of the second differential amplifier is a relatively low-voltage level with respect to ground; said first condition at the output connection of the first NAND gate of the bistable circuit means is a relatively high-voltage level with respect to ground and the second condition at the output connection of the first NAND gate of the bistable circuit means is a relatively low-voltage level with respect to ground; said first condition at the output connection of the second NAND gate of the bistable circuit means is a relatively voltage level with respect to ground and the second condition at the output connection of the second NAND gate of the bistable circuit means is a relatively low-voltage level with respect to ground; said first condition at the output of the inverter circuit is a relatively high-voltage level with respect to ground and the second condition at the output of the inverter circuit is a relatively low-voltage level with respect to ground; and said first condition at the output of the NAND gate of the output means is a relatively high-voltage level with respect to ground and the second condition at the output of the NAND gate of the output means is a relatively low-voltage level with respect to ground.
Claim 8
Dependent Claim
38 words
A limiter circuit in accordance with claim 6 wherein said first and second differential amplifiers are each differential voltage comparators with the first input terminals being noninverting input terminals and the second input terminals being inverting input terminals.
References Cited (Backward Citations)
US3579125A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-31 | 1975-08-02 | 1976-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-31 | 1979-08-02 | 1980-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-31 | 1983-08-02 | 1984-02-01 | $7700.00 | Window Closed / Lapsed |