Abstract Apparatus for resetting an analog integrator with digital readout capability. The resetting signal, which discharges the integrating capacitor, is terminated when the output of the integrator reaches a level which is proportional to the analog input signal instead of completely discharging the integrating capacitor. This compensates for the errors present in prior art analog integrators caused by ignoring the analog input signal during the discharge time of the integrating capacitor. During the discharge of the integrating capacitor, an operational amplifier compares the integrator output voltage with a signal proportional to the analog input signal, called the compensating voltage. When two signals are equal the resetting signal is terminated.
Apparatus for resetting an analog integrator providing digital readout of an analog signal, such digital integrator comprising an operational amplifier, including an integrating capacitor, arranged to operate as an integration amplifier to convert an analog input signal into an output signal varying between two limit values and means responsive to the output signal for initiating, at the upper limit value of said output signal, a resetting signal for feeding back into the input of said integration amplifier at a polarity opposite to that of the input signal to cause discharge of said integration capacitor connected to said input, in which apparatus a second operational amplifier forming a part of said analog integrator is arranged to interrupt said resetting signal when the output signal of said integration amplifier reaches its lower limit value corresponding to a compensation signal which is directly proportional to said input signal during the occurrence of said resetting signal.
Claim 2
Dependent Claim
152 words
Apparatus for resetting an analog integrator providing digital readout of an analog signal, such digital integrator comprising an operational amplifier, including an integrating capacitor, arranged to operate as an integration amplifier to convert an analog input signal into an output signal varying between two limit values and means responsive to the output signal for initiating, at the upper limit value of said output signal, a resetting signal for feeding back into the input of said integration amplifier at a polarity opposite to that of the input signal to cause discharge of said integration capacitor connected to said input, in which apparatus a second operational amplifier forming a part of said analog integrator is arranged to interrupt said resetting signal when the output signal of said integration amplifier reaches its lower limit value corresponding to a compensation signal which is directly proportional to said input signal during the occurrence of said resetting signal.