Patent US3766472A successfully refreshed from Google Patents.
US3766472A
Expired / Lapsed
US
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Apparatus for elimination of error in a detecting system
Assignee: Franklin Electric Co Inc
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Filing: 1971-11-02
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Granted: 1973-10-16
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Expires: 1991-11-02
Abstract
Abstract This disclosure deals with a system wherein the frequency of a signal having a variable frequency representative of a parameter is measured in order to make a determination of the parameter. The frequency of the signal is measured during a normal measuring mode of operation by counting the number of cycles of the signal occurring within a fixed time base. Prior to the normal measuring mode of operation, the operator initiates a set zero mode of operation, wherein the resolution of the measurement is increased by a predetermined ratio. At this increased resolution, any portion of a cycle, which is present but which would not be counted during the normal measuring mode of operation, is detected and is utilized to actuate a circuit for adjusting the frequency. The frequency is adjusted either upwardly or downwardly so that an integral number of whole cycles occurs during the time base, thereby eliminating said portion of a cycle.
Inventors
- 👤 J Whitney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:09
CPC Classifications
G; G01; G01G; G01G23/00; G01G23/18; G01G23/36; G01G23/37
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
207 words
A system comprising a source of a variable frequency signal, the frequency representing a parameter and the frequency having a finite value when said parameter is zero, a source of a time base signal, first register means for counting the number of cycles of said variable frequency signal occurring during said time base signal, second register means for storing said finite value, means responsive to said variable frequency signal and to said second register means for subtracting said finite value from said variable frequency signal before said variable frequency signal is fed to said first register means, and rounding means for adjusting the frequency of said variable frequency signal upwardly or downwardly to cause said finite value to consist of an integral number of cycles of said variable frequency signal, said rounding means comprising resolution increasing means for multiplying one of said signals relative to the other, means responsive to said mulitplied signal for sensing at said increased resolution any portion of a cycle of said finite value which is not stored in said second register means, and adjusting means responsive to said portion sensing means for adjusting the frequency of said variable frequency signal to round said portion upwardly or downwardly to the nearest full cycle.
Claim 2
Independent Claim
207 words
A system comprising a source of a variable frequency signal, the frequency representing a parameter and the frequency having a finite value when said parameter is zero, a source of a time base signal, first register means for counting the number of cycles of said variable frequency signal occurring during said time base signal, second register means for storing said finite value, means responsive to said variable frequency signal and to said second register means for subtracting said finite value from said variable frequency signal before said variable frequency signal is fed to said first register means, and rounding means for adjusting the frequency of said variable frequency signal upwardly or downwardly to cause said finite value to consist of an integral number of cycles of said variable frequency signal, said rounding means comprising resolution increasing means for multiplying one of said signals relative to the other, means responsive to said mulitplied signal for sensing at said increased resolution any portion of a cycle of said finite value which is not stored in said second register means, and adjusting means responsive to said portion sensing means for adjusting the frequency of said variable frequency signal to round said portion upwardly or downwardly to the nearest full cycle.
Claim 3
Dependent Claim
116 words
A circuit for reducing error in a frequency responsive system including a source of a variable frequency signal and a source of a time base signal, said system operating by counting the number of cycles of said signal occurring within a time base signal, said circuit comprising resolution increasing means connected to one of said sources for multiplying by a predetermined factor the number of said cycles occurring in a time base, circuit means connected to receive said multiplied number of cycles and determining the number of cycles in excess of an integral multiple of said factor, and adjusting means responsive to said excess for changing the frequency of said signal to substantially eliminate said excess.
Claim 4
Dependent Claim
116 words
A circuit for reducing error in a frequency responsive system including a source of a variable frequency signal and a source of a time base signal, said system operating by counting the number of cycles of said signal occurring within a time base signal, said circuit comprising resolution increasing means connected to one of said sources for multiplying by a predetermined factor the number of said cycles occurring in a time base, circuit means connected to receive said multiplied number of cycles and determining the number of cycles in excess of an integral multiple of said factor, and adjusting means responsive to said excess for changing the frequency of said signal to substantially eliminate said excess.
Claim 5
Dependent Claim
23 words
A circuit as in claim 2, wherein said resolution increasing means multiplies the time duration of said time base signal by said factor.
Claim 6
Dependent Claim
61 words
A circuit as in claim 3, wherein said source of said time base signal comprises an oscillator and a time base circuit which responds to the frequency of said oscillator, said resolution increasing means comprising a circuit connected between said oscillator and said time base circuit for decreasing by said factor the frequency of the signal to said time base circuit.
Claim 7
Dependent Claim
70 words
A circuit as in claim 2, wherein said circuit means includes a counter having a capacity equal to said factor, said counter producing an output signal each time said counter receives a number of cycles equal to said factor, and means responsive to a residual count in said counter at the end of said time base for actuating said adjusting means, said residual count being equivalent to said excess cycles.
Claim 8
Dependent Claim
25 words
A circuit as in claim 5, wherein said factor is ten, and said counter includes four flip-flops connected to have a counting capacity of ten.
Claim 9
Dependent Claim
26 words
A circuit as in claim 6, wherein said adjusting means comprises four electromagnets, said electromagnets being energized respectively in response to the states of said flip-flops.
Claim 10
Independent Claim
159 words
A system for measuring a parameter which is represented by an analog quantity, said quantity having a finite value when the parameter is zero, comprising zero setting means responsive to said quantity during a zero setting mode of operation and converting said quantity to a digital signal form consisting of a first plurality of pulses, said zero setting means further including adjusting means and memory means, said adjusting means being responsive to said first plurality of pulses and adjusting said parameter and thereby said analog quantity until said first plurality of pulses is an integral number of whole pulses, and said memory means storing said integral number, said system further comprising normal measuring means responsive to said quantity during a normal measuring mode of operation and converting said quantity to a digital signal form consisting of a second plurality of pulses, and means subtracting said first and second pluralities of pulses to obtain an accurate measurement of said parameter.
Claim 11
Independent Claim
159 words
A system for measuring a parameter which is represented by an analog quantity, said quantity having a finite value when the parameter is zero, comprising zero setting means responsive to said quantity during a zero setting mode of operation and converting said quantity to a digital signal form consisting of a first plurality of pulses, said zero setting means further including adjusting means and memory means, said adjusting means being responsive to said first plurality of pulses and adjusting said parameter and thereby said analog quantity until said first plurality of pulses is an integral number of whole pulses, and said memory means storing said integral number, said system further comprising normal measuring means responsive to said quantity during a normal measuring mode of operation and converting said quantity to a digital signal form consisting of a second plurality of pulses, and means subtracting said first and second pluralities of pulses to obtain an accurate measurement of said parameter.
Claim 12
Dependent Claim
16 words
A system as in claim 8, wherein said analog quantity is the frequency of a signal.
Claim 13
Dependent Claim
17 words
A signal as in claim 8 wherein said analog quantity is the position of a movable member.
References Cited (Backward Citations)
US3665169A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-15 | 1977-04-16 | 1977-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-15 | 1981-04-16 | 1981-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-15 | 1985-04-16 | 1985-10-16 | $7700.00 | Window Closed / Lapsed |