US3766432A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Actuator drive circuitry for producing dual level drive current
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1972-10-20
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Granted: 1973-10-16
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Expires: 1992-10-20
Abstract
Abstract Drive circuitry for a bi-directional solenoid actuator having first and second coils which are energized during mutually exclusive and complementary time periods. Each coil is in circuit with a low impedance bypass which is effective only for a short time after energization of the associated coil. While the bypass is effective, a relatively high current is applied to the coil to seat the solenoid core. When the bypass is rendered ineffective, a relatively lower current is applied to the coil to hold the core in place. The circuitry also includes normally back-biased diodes which are driven to a forward-biased state upon coil deenergization to connect voltage sources to the coil to limit induced voltages to accelerate current decay in the de-energized coil.
Inventors
- 👤 I Markowitz
- 👤 E Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:41
CPC Classifications
H; H01; H01H; H01H47/00; H01H47/02; H01H47/04
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
356 words
Drive circuitry for a solenoid actuator having first and second coils energizable during mutually exclusive and complementary periods of time as a function of the level of a binary control signal including: a. a pulse generating circuit connected to the binary control signal source and responsive to any logic level change in the control signal to generate a primary limited duration pulse; b. a first logic circuit connected to the output of the pulse generating circuit and in circuit with the control signal source to generate a first limited duration pulse only when the control signal changes to a first logic level; c. a second logic circuit connected to the output of the pulse generating circuit and in circuit with the control signal source to generate a second limited duration pulse only when the binary control signal changes to a second logic level; d. a first current control circuit for the first coil comprising i. a first driving voltage source, ii. a first switching circuit connected in series with the first driving voltage source and the first coil, said switching circuit being responsive to the control signal being at its first level to complete a current path from the voltage source through the first coil, and iii. a first low impedance bypass circuit connected to the output of the first logic circuit and in parallel with part of the switching circuit to reduce the impedance of the completed current path for the duration of the first limited duration pulse; e. a second current control circuit for the second coil comprising i. a second driving voltage source, ii. a second switching circuit connected in series with the second driving voltage source and the second coil, said switching circuit being responsive to the control signal being at its second level to complete a current path from the voltage source through the second coil, and iii. a second low iMpedance bypass circuit connected to the output of the second logic circuit and in parallel with part of the second switching circuit to reduce the impedance of the completed current path for the duration of the second limited duration pulse.
Claim 2
Dependent Claim
356 words
Drive circuitry for a solenoid actuator having first and second coils energizable during mutually exclusive and complementary periods of time as a function of the level of a binary control signal including: a. a pulse generating circuit connected to the binary control signal source and responsive to any logic level change in the control signal to generate a primary limited duration pulse; b. a first logic circuit connected to the output of the pulse generating circuit and in circuit with the control signal source to generate a first limited duration pulse only when the control signal changes to a first logic level; c. a second logic circuit connected to the output of the pulse generating circuit and in circuit with the control signal source to generate a second limited duration pulse only when the binary control signal changes to a second logic level; d. a first current control circuit for the first coil comprising i. a first driving voltage source, ii. a first switching circuit connected in series with the first driving voltage source and the first coil, said switching circuit being responsive to the control signal being at its first level to complete a current path from the voltage source through the first coil, and iii. a first low impedance bypass circuit connected to the output of the first logic circuit and in parallel with part of the switching circuit to reduce the impedance of the completed current path for the duration of the first limited duration pulse; e. a second current control circuit for the second coil comprising i. a second driving voltage source, ii. a second switching circuit connected in series with the second driving voltage source and the second coil, said switching circuit being responsive to the control signal being at its second level to complete a current path from the voltage source through the second coil, and iii. a second low iMpedance bypass circuit connected to the output of the second logic circuit and in parallel with part of the second switching circuit to reduce the impedance of the completed current path for the duration of the second limited duration pulse.
Claim 3
Dependent Claim
131 words
A control circuit as recited in claim 1 wherein each of said first and second driving voltage sources has a first polarity and each of said first and second switching circuits further includes: a. a decay voltage source having a second polarity; b. a first diode having one terminal connected to the end of the coil adjacent said driving voltage source and the other terminal connected to the decay voltage source, said first diode being normally back biased; c. a second diode having one terminal connected to the other end of the coil and the other terminal connected to the driving voltage source, said second diode also being normally back biased; d. said first and second diodes being forward biased by the voltage induced across the coil immediately following coil deenergization.
Claim 4
Dependent Claim
108 words
A control circuit as recited in claim 1 wherein each of said first and second switching circuits further comprises: a. a first transistor having its emitter and collector terminals connected in series between the driving voltage source and one end of the associated coil and its base terminal connected in circuit with the binary control signal source; b. an impedance connected in series at the other end of the coil; and c. a second transistor having its emitter and collector terminals connected in series between the other end of the coil and a reference voltage terminal and its base terminal connected in circuit with the associated logic circuit.
Claim 5
Dependent Claim
109 words
A control circuit as recited in claim 2 wherein each of said first and second switching circuits further comprises: a. a first transistor having its emitter and collector terminals connected in series between the driving voltage source and one end of the associated coil and its base terminal connected in circuit with the binary control signal source; b. an impedance connected in series at the other end of the coil; and c. a second transistor having its emitter and collector terminals connected in series between the lower end of the impedance and a reference voltage terminal and its base terminal connected in circuit with the binary control signal source.
Claim 6
Dependent Claim
75 words
A control circuit as recited in claim 3 wherein each of said low impedance bypass circuits comprises a third transistor having its emitter and collector terminals connected in series between said other end of said coil and the reference voltage terminal and its base terminal connected to the output of the associated logic circuit, said third transistor being biased into conduction for the duration of the limited duration pulse produced by said associated logic circuit.
Claim 7
Dependent Claim
75 words
A control circuit as recited in claim 4 wherein each of said low impedance bypass circuits comprises a third transistor having its emitter and collector terminals connected in series between said other end of said coil and the reference voltage terminal and its base terminal connected to the output of the associated logic circuit, said third transistor being biased into conduction for the duration of the limited duration pulse produced by said associated logic circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-15 | 1977-04-16 | 1977-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-15 | 1981-04-16 | 1981-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-15 | 1985-04-16 | 1985-10-16 | $7700.00 | Window Closed / Lapsed |