Electronic combination lock

Claim 2

Combination lock circuitry for controlling energization of an electrical load device in response to entry of a predetermined combination code, said lock circuitry comprising: a plurality of operator-actuable input switch means for entering the combination code; a multistage serial shift register having a data input, a clock input, and an initializing input; reset means connected to said initializing input for resetting the output of each stage of said register to a first of two logic levels; clock generating means interconnecting said input switch means with said clock input for developing a clock pulse in response to actuation of any one of said input switch means; a plurality of AND function performing gate means, the first of said AND gates being connected with the input switch means associated with the first symbol of said code, successive ones of said AND gates being connected with respective ones of said input switch means associated with successive symbols in said code; means connecting the output of each of said AND gates with the data input of said register; means connecting the output of certain stages of said register as inputs to certain of said AND gates to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates; means for inhibiting said clock means whenever the output of the first stage of said register is at said first logic level and the output of the second stage of said register is at the other logic level; and means responsive to the output of the first and nth (where n the number of symbols in the code) stage of said register for energizing said electrical load device when the outputs of the first and nth stage of said register are at said other logic level.

Claim 3

The circuitry defined in claim 1 further including select gate means connected between said switch means and said AND gates for selecting one or the other of two combination codes, said select gate means adapted to select one of said codes in response to simultaneous actuation of certain of said switch means and to select the other of said codes in response to entry of the first of said codes and simultaneous actuation of certain other of said switch means.

Claim 4

In a motor vehicle provided with a source of direct current and an ignition switch connected therewith: electrical load means for preventing normal operation of said vehicle until energized; electronic combination lock circuitry adapted to be connected with said source for energizing said load means in response to entry of a PRIMARY or a TURNOVER combination code; said lock circuitry including a plurality of operator actuable input switch means for entering the combination codes; a multistage shift register having a plurality of flip-flops, each flip-flop including a clock input, a data input, a reset input and an output, the output of each flip-flop being connected with the data input of the succeeding flip-flop; means connecting said ignition switch to said reset inputs for resetting the output of each flip-flop of said register to a logic 0 level in response to opening of said ignition switch; clock generator means interconnecting said input switch means with said clock inputs for developing a clock pulse in response to actuation of any one of said input switch means for transferring the logic level at the data input of each flip-flop to the output thereof; sequence control means including a plurality of AND function performing gate means, OR function performing means having its inputs connected with the outputs of said AND gates and its output connected with the data input of the first flip-flop of said register; a mode flip-flop for developing a first output in response to simultaneous actuation of certain of said input switch means and for developing a second output in response to entry of said PRIMARY code and simultaneous actuation of certain others of said input switch means; select gate means responsive to the outputs of said mode flip-flop for connecting one or the other of two groups of input switch means associated with said PRIMARY code or said TURNOVER code respectively to said AND gates, the first of said AND gate means being connected with the input switch means associated with the first symbol of said codes, successive ones of said AND gates being connected with respective ones of the input switch means associated with successive symbols in said codes; means connecting the output of certain flip-flops of said register as inputs to certain of said AND gates to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates; means for inhibiting said clock generator means whenever the output of the first stage of said register is a logic 0 and the output of the second stage of said register is a logic 1; and means responsive to the output of the first and nth (where n the number of symbols in the code) flip-flop of said register for energizing said electrical load device when the output of the first and nth flip-flop of said register are at a logic 1.

Claim 5

In a motor vehicle provided with a source of direct current and an ignition switch connected therewith: electrical load means for preventing normal operation of said vehicle until energized; electronic combination lock circuitry adapted to be connected with said source for energizing said load means in response to entry of a PRIMARY or a TURNOVER combination code; said lock circuitry including a plurality of operator actuable input switch means for entering the combination codes; a multistage shift register having a plurality of flip-flops, each flip-flop including a clock input, a data input, a reset input and an output, the output of each flip-flop being connected with the data input of the succeeding flip-flop; means connecting said ignition switch to said reset inputs for resetting the output of each flip-flop of said register to a logic 0 level in response to opening of said ignition switch; clock generator means interconnecting said input switch means with said clock inputs for developing a clock pulse in response to actuation of any one of said input switch means for transferring the logic level at the data input of each flip-flop to the output thereof; sequence control means including a plurality of AND function performing gate means, OR function performing means having its inputs connected with the outputs of said AND gates and its output connected with the data input of the first flip-flop of said register; a mode flip-flop for developing a first output in response to simultaneous actuation of certain of said input switch means and for developing a second output in response to entry of said PRIMARY code and simultaneous actuation of certain others of said input switch means; select gate means responsive to the outputs of said mode flip-flop for connecting one or the other of two groups of input switch means associated with said PRIMARY code or said TURNOVER code respectively to said AND gates, the first of said AND gate means being connected with the input switch means associated with the first symbol of said codes, successive ones of said AND gates being connected with respective ones of the input switch means associated with successive symbols in said codes; means connecting the output of certain flip-flops of said register as inputs to certain of said AND gates to enable said first AND gate and disable the remaining AND gates when said register is reset and to sequentially enable said successive ones of said AND gates and sequentially disable the preceding AND gate upon actuation of the input switch means associated with the enabled gates; means for inhibiting said clock generator means whenever the output of the first stage of said register is a logic 0 and the output of the second stage of said register is a logic 1; and means responsive to the output of the first and nth (where n the number of symbols in the code) flip-flop of said register for energizing said electrical load device when the output of the first and nth flip-flop of said register are at a logic 1.

Claim 6

The circuitry defined in claim 3 further including indicator means; time delay means for maintaining a logic level output for a predetermined interval of time subsequent to opening of said ignition switch; additional AND function performing gate means responsive to the output of said time delay means and to resetting of said register for energizing said indicator for said predetermined time interval to indicate to the operator that said electrical load means is deenergized.