Electronic combination lock system

Claim 2

A electronic combination lock system comprising, in combination: input means for providing control signals for said system, said control signals including a sequence of digit signals representing a combination; a decoder including coding means for establisHing a predetermined combination of digits for said system, means for comparing said digit signals with respective digits of said predetermined combination and producing an output signal in response thereto, said comparing means including first means for determining the value of each of said digit signals and second means for determining the sequential position of each of said digit signals such that each of said digit signals can be compared to the corresponding digit in said predetermined combination; and locking means responsive to said output signal for moving between locked and unlocked positions.

Claim 3

Apparatus in accordance with claim 1 wherein said first and second determining means comprise first and second counters, respectively.

Claim 4

Apparatus in accordance with claim 2 including a first series of AND gates connected to said first counter, one of said first series of gates responding to said first counter according to said value of said digit signal, a second series of AND gates connected to said second counter, one of said second series of gates responding to said second counter according to said sequential position.

Claim 5

Apparatus in accordance with claim 3 wherein said coding means interconnects said first and second series of AND gates such that said predetermined combination of digits is established, said one of said second series of AND gates produces an output when said digit signal compares with said respective digit of said predetermined combination.

Claim 6

Apparatus in accordance with claim 4 including third means for determining the number of said outputs from said second series of AND gates and producing said output signal when said number of outputs equals the number of digits in said predetermined combination.

Claim 7

Apparatus in accordance with claim 5 wherein said third determining means comprises a third counter for counting said number of outputs and an AND gate responsive to said counter for producing said output signal.

Claim 8

Apparatus in accordance with claim 6 wherein said first, second, and third counters comprise flip-flop circuits.

Claim 9

Apparatus in accordance with claim 6 including means for resetting said second and third counters to respective initial sets whenever the number of said digit signals exceeds said number of digits in said predetermined combination.

Claim 10

Apparatus in accordance with claim 8 wherein said resetting means includes a gate of said second series which produces a trigger output in response to said second counter whenever said second counter registers a number greater than said number of digits in said predetermined combination, and a flip-flop circuit which produces a pulse in response to said trigger output to reset said second and third counters.

Claim 11

Apparatus in accordance with claim 6 wherein said control signals include an initializing signal for setting said second and third counters to respective initial sets before and after said sequence of digit signals is provided.

Claim 12

Apparatus in accordance with claim 6 wherein said control signals include a spacing signal interspersed between each of said digit signals, said spacing signal resetting said first counter to an initial state and advancing said second counter one count after each digit signal of said sequence is provided.

Claim 13

Apparatus in accordance with claim 5 including means for delaying said outputs from said second series of gates, said third determining means selectively responding to said outputs which have a duration greater than the delay time of said delaying means such that a minumum time for operating said lock system is established.

Claim 14

Apparatus in accordance with claim 1 including means for rejecting any digit signals having a value greater than the value of the largest of said digits in said predetermined combination.

Claim 15

Apparatus in accordance with claim 13 wherein said rejecting means comprises an AND gate responsive to said first determining means for producing an output whenever said first determiniNg means indicates a value greater than said value of said largest of said digits, said second determining means being responsive to said output to change said sequential position.

Claim 16

Apparatus in accordance with claim 1 wherein said locking means comprises a locking bar movable between said locked and unlocked positions, and power means for moving said bar.

Claim 17

Apparatus in accordance with claim 15 wherein said power means comprises a solenoid.

Claim 18

Apparatus in accordance with claim 1 wherein said control signals include an initializing signal for setting said decoder to an initial state before and after said sequence of digits is provided.

Claim 19

Apparatus in accordance with claim 17 wherein said initializing signal sets said second determining means to an initial state.

Claim 20

Apparatus in accordance with claim 1 wherein said control signals include a spacing signal interspersed between each digit signal of said sequence, said spacing signal resetting said first determining means to an initial state and causing said second determining means to indicate a different sequential position after each digit signal is provided.

Claim 21

Apparatus in accordance with claim 19 wherein said spacing signals and said digit signals comprise respective positive and negative pulses on a single conductor from said input means, said decoder including an interface connected to said input means for separating said spacing and said digit signals.

Claim 22

Apparatus in accordance with claim 19 wherein said decoder includes an AND gate for producing an initializing signal whenever said spacing signal and said digit signal coincide, said initializing signal operating to reset said decoder to an initial state.

Claim 23

An electronic combination lock system comprising, in combination: a coding matrix for establishing a predetermined combination of digits for said system; input means for providing a sequence of digit signals for comparison with said digits of said predetermined combination; a first counter including a series of flip-flop circuits for determining the value of each of said digit signals; a second counter including a series of flip-flop circuits for determining the sequential position of each of said digit signals; comparing means including first and second series of AND gates connected to said first and second counters, respectively, for sequentially comparing said digit signals with respective digits of said predetermined combination and producing an output whenever a digit signal equals said respective digit; a third counter comprising a series of flip-flop circuits for counting said outputs; an AND gate responsive to said third counter for producing an output signal when said third counter registers a value equal to the number of digits in said predetermined combination; and locking means responsive to said output signal for moving between locked and unlocked positions.

Claim 24

An electronic combination lock system comprising, in combination: a coding matrix for establishing a predetermined combination of digits for said system; input means for providing a sequence of digit signals for comparison with said digits of said predetermined combination; a first counter including a series of flip-flop circuits for determining the value of each of said digit signals; a second counter including a series of flip-flop circuits for determining the sequential position of each of said digit signals; comparing means including first and second series of AND gates connected to said first and second counters, respectively, for sequentially comparing said digit signals with respective digits of said predetermined combination and producing an output whenever a digit signal equals said respective digit; a third counter comprising a series of flip-flop circuits for counting said outputs; an AND gate responsive to said third counter for producing an output signal when said third counter registers a value equal to the number of digits in said predetermined combination; and locking means responsive to said output signal for moving between locked and unlocked positions.

Claim 25

Apparatus in accordance with claim 22 wherein said input means provides a first control signal for setting said second and third counters to respective initial states before and after each sequence of digit signals is provided, and a second control signal for resetting said first counter to an initial state after each of said digit signals is provided.

Claim 26

Apparatus in accordance with claim 22 wherein said input means provides power for operating said lock system.